73M1903C-IM 查看數據表（PDF） - Teridian Semiconductor Corporation

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73M1903C-IM

Modem Analog Front End

Teridian Semiconductor Corporation 

73M1903C

Modem Analog Front End

DATA SHEET

INTLB

CkoutEn

RXPULL

SPOS

HC

(0X01[4]) Internal Loop back Enable. (Remote Analog Loop back)

0 = Normal operation

1 = Tie the digital serial bit stream from the analog receiver output to the analog transmitter

input.

(0X01[3]) Clock Output Enable

1 = Enable the CLKOUT output; This bit must be set after the FSDEn bit is set to enable

daisy chain mode.

0 = CLKOUT tri-stated, for normal operation.

(0X01[2])

1 = Pulls DC Bias to RXAP/RXAN pins, thru 100Kohm each, to VREF, to be used in

testing Rx path.

0 = No DC Bias to RXAP/RXAN pins

(0X01[1])

1 = Control frames occur after one quarter of the time between data frames has elapsed.

0 = Control frames occur half way between data frames.

(0X01[0])

1 = Control frame generation is under hardware control, bit 0 of data frames on SDIN is bit

0 of the transmit word and control frames happen automatically after every data frame.

0 = Control frame generation is under software control, bit 0 of data frames on SDIN is a

control frame request bit and control frames happen only on request.

Register06 (REV): Address 06h

Reset State 60h

BIT 7

BIT 6

BIT 5

BIT 4

Rev(3:0)

BIT 3

FSDEn

BIT 2

BIT 1

BIT 0

Reserved

Rev(3:0)

FSDEn

(0X06[7:4]) Contain the revision ID of the TERIDIAN 73M1903C device. The rest of this

register is for chip development purposes only and is not intended for customer use. Do not

write to shaded locations.

(0X06[3]) Delayed Frame Sync Enable. This bit shall be enabled if the daisy chain mode is

used.

1 = Delayed frame sync for daisy chaining of additional 73M1903C devices.

0 = FSD tristated, for normal operation.

GPIO REGISTERS

The TERIDIAN 73M1903C modem AFE device provides 8 user definable I/O pins. Each pin is

programmed separately as either an input or an output by a bit in a direction register. If the bit in the

direction register is set high, the corresponding pin is an input whose value is read from the GPIO data

register. If it is low, the pin will be treated as an output whose value is set by the GPIO data register.

To avoid unwanted current contention and consumption in the system from the GPIO port before the

GPIO is configured after a reset, the GPIO port I/Os are initialized to a high impedance state. The input

structures are protected from floating inputs, and no output levels are driven by any of the GPIO pins.

The GPIO pins are configured as inputs or outputs when the host controller (or DSP) writes to the GPIO

direction register. The GPIO direction and data registers are initialized to all ones (FFh) upon reset.

Page: 13 of 46

© 2005-2008 TERIDIAN Semiconductor Corporation

Rev 4.3

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