73M1903C-IMR 查看數據表（PDF） - Teridian Semiconductor Corporation
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73M1903C-IMR Datasheet PDF : 46 Pages
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73M1903C
Modem Analog Front End
DATA SHEET
Register02 (DATA): Address 02h
Reset State FFh
BIT 7
BIT 6
BIT 5
BIT 4
GPIO7 GPIO6 GPIO5 GPIO4
BIT 3
GPIO3
BIT 2
GPIO2
BIT 1
GPIO1
BIT 0
GPIO0
GPIO(7:0)
(0X02[7:0])
Bits in this register will be asserted on the GPIO(7:0) pins if the
corresponding direction register bit is a 0. Reading this address will return data reflecting
the values of pins GPIO(7:0).
Register03 (DIR): Address 03h
Reset State FFh
BIT 7
BIT 6
BIT 5
BIT 4
DIR7
DIR6
DIR5
DIR4
BIT 3
DIR3
BIT 2
DIR2
BIT 1
DIR1
BIT 0
DIR0
DIR(7:0)
(0X03[7:0])
This register is used to designate the GPIO pins as either inputs or
outputs. If the register bit is reset to ‘0’, the corresponding GPIO pin is programmed as an
output. If the register bit is set to a “1”, the corresponding pin will be configured as an input.
PLL CONFIGURATION REGISTERS
Register08 (PLL_PSEQ): Address 08h
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Pseq(7:0)
BIT 2
BIT 1
BIT 0
Pseq(7:0) (0X08[7:0])
This corresponds to the sequence of divisor. If Prst(2:0) setting in
Register09 is 00, this register is ignored.
Register09 (PLL_RST): Address 09h
Reset State 0Ah
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Prst(2:0)
Pdvsr(4:0)
Prst(2:0) represents the rate at which the sequence register is reset.
Pdvsr(4:0) represents the divisor.
BIT 1
BIT 0
Register0A (PLL_KVCO): Address 0Ah
Reset State 22h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Ichp(3:0)
Reserved
BIT 2
BIT 1
Kvco(2:0)
BIT 0
Ichp(3:0) (0X0A[:47]) represents the size of the charge pump current in the PLL. This charge pump
current can be calculated with Ichp = 2.0µA* (2 + Ichp0 + Ichp1 * 21 + Ichp2 * 22+Ichp3 * 2^3 )*
(T/To), where To=300 C° and T=Temperature in K°.
Bit 3 is a reserved control bit. This bit shall remain “0” always.
Kvco(2:0) (0X0A[2:0]) Represents the magnitude of Kvco associated with the VCO within PLL.
Page: 14 of 46
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
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