73M1903C-IM/F 查看數據表（PDF） - Teridian Semiconductor Corporation
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73M1903C-IM/F Datasheet PDF : 46 Pages
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73M1903C
Modem Analog Front End
DATA SHEET
Kvco2
0
0
0
0
1
1
1
1
Kvco1
0
0
1
1
0
0
1
1
Kvco0
0
1
0
1
0
1
0
1
Fvco
33 MHz
36 MHz
44 MHz
48 MHz
57 MHz
61 MHz
69 MHz
73 MHz
Table 3: Fvco and Kvco settings at 25°C
Kvco
38MHz/v
38MHz/v
40MHz/v
40MHz/v
63MHz/v
63MHz/v
69MHz/v
69MHz/v
Register0B (PLL_DIV): Address 0Bh
Reset State 12h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
Ndvsr(6:0)
BIT 2
BIT 1
BIT 0
Ndvsr(6:0) (0X0B[6:0]) Represents the divisor. If Nrst{2:0] =0 this register is ignored.
Register0C (PLL_SEQ): Address 0Ch
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Nseq(7:0)
BIT 2
BIT 1
BIT 0
Nseq(7:0)
(0X0C[7:0]) Represents the divisor sequence.
Register0D (XTAL_BIAS): Address 0Dh
Reset State 48h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Xtal(1:0)
Reserved
-
BIT 2
BIT 1
Nrst(2:0)
BIT 0
Xtal(1:0)
Nrst(2:0)
(0X0D[7:6]) Crystal Oscillator bias current selection
00 = Xtal osc. bias current at 120µA
01 = Xtal osc. bias current at 180µA
10 = Xtal osc. bias current at 270µA
11 = Xtal osc. bias current at 450µA
If OSCIN is used as a Clock input, “00” setting should be used to save power.
(0X0D[2:0]) Represents the rate at which the NCO sequence register is reset.
The address 0Dh must be the last register to be written to when effecting a change in PLL.
Page: 15 of 46
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
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