73S8009C-32IMR/F 查看數據表（PDF） - Teridian Semiconductor Corporation

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73S8009C-32IMR/F

Versatile Power Management and Smart Card Interface IC

Teridian Semiconductor Corporation 

73S8009C Data Sheet

DS_8009C_025

Symbol

Parameter

Condition

Reset and Clock for card interface, RST, CLK

VOH

Output level, high

IOH =-200 µA

VOL

Output level, low

IOL=200 µA

VINACT

IRST_LIM

ICLK_LIM

tR, tF

Output voltage when

outside of session

Output current limit, RST

Output current limit, CLK

Output rise time, fall time

δ

Duty cycle for CLK

IOL = 0

CL = 35pF for CLK, 10% to

90%

CL = 200pF for RST, 10% to

90%

CL =35pF, FCLK ≤ 20 MHz,

CLKIN duty cycle is 48% to

52%.

Min Nom Max

0.9 * VCC

–

0

–

–

–

–

–

–

–

–

–

–

–

45

–

VCC

0.15

*VCC

0.1

30

70

12

100

55

Unit

V

V

V

mA

mA

ns

ns

%

2.4 Digital Signals Characteristics

Table 5 lists the 73S8009C digital signals characteristics.

Table 5: Digital Signals Characteristics

Symbol Parameter

Condition

Min

Nom Max

Unit

Digital I/O

(except for I/OUC, AUX1UC, AUX2UC; see Smart Card Interface Requirements for those specifications)

VIL

Input Low Voltage

-0.3

–

0.8

V

VILOFFACK Input low voltage for

OFF_REQ pin = VDD

-0.3

–

0.7

V

OFF_ACK pin

VIH

VOL

VOH

ROUT

Input High Voltage

Output Low Voltage

Output High Voltage

Pull-up resistor; OFF, RDY

IOL = 2 mA

IOH = -1 mA

1.8

– VDD + 0.3

V

–

0.45

V

VDD - 0.45 –

V

14

20

26

kΩ

RACK

Resistor between

OFF_REQ and 0FF_ACK

70

100

130

kΩ

|IIL1|

Input Leakage Current

GND < VIN < VDD

tSL

Time from CS goes high to

interface active

–

–

5

μA

50

–

–

ns

tDZ

Time from CS goes low to

interface inactive, Hi-Z

50

–

–

ns

tIS

Set-up time, control

signals to CS rising edge

50

–

–

ns

tSI

Hold time, control signals

from CS rising edge

–

–

50

ns

tID

Set-up time, control

signals to CS fall

50

–

–

ns

tDI

Hold time, control signals

from CS fall

–

–

50

ns

14

Rev. 1.4

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