73S8014RT 查看數據表（PDF） - Teridian Semiconductor Corporation

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73S8014RT

Smart Card Interface

Teridian Semiconductor Corporation 

73S8014RT Data Sheet

DS_8014RT_015

3.8 Fault Detection and OFF

There are two different cases that the system controller can monitor the OFF signal: to query regarding the card

presence outside card sessions, or for fault detection during card sessions.

Outside a card session: In this condition, CMDVCC% and CMDVCC# are always high, OFF is low if the card is not

present, and high if the card is present. Because it is outside a card session, any fault detection will not act upon

the OFF signal. No deactivation is required during this time.

During a card session: CMDVCC% or CMDVCC# is/are always low, and OFF falls low if the card is extracted or if

any fault detection is detected. At the same time that OFF is set low, the sequencer starts the deactivation

process.

Figure 7 shows the timing diagram for the signals CMDVCC% or CMDVCC#, PRES, and OFF during a card

session and outside the card session:

Figure 7: Timing Diagram – Management of the Interrupt Line OFF

3.9 I/O Circuitry and Timing

The state of the I/O pin is low after power on reset and it goes high when the activation sequencer turns on the

I/O reception state. See the Activation Sequence section for details on when the I/O reception is enabled. The

state of I/OUC is high after power on reset.

Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling edge is

detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising

edge is detected then both I/O lines return to their neutral state.

Figure 8 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output. The

delay between the I/O signals is shown in Figure 9.

20

Rev. 1.0

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