74F676SC 查看數據表（PDF） - Fairchild Semiconductor
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74F676SC Datasheet PDF : 6 Pages
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Unit Loading/Fan Out
Pin Names
Description
P0–P15
CS
CP
M
SI
SO
Parallel Data Inputs
Chip Select Input (Active LOW)
Clock Pulse Input (Active LOW)
Mode Select Input
Serial Data Input
Serial Output
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
Functional Description
The 16-bit shift register operates in one of three modes, as
indicated in the Shift Register Operations Table.
HOLD— a HIGH signal on the Chip Select (CS) input pre-
vents clocking, and data is stored in the sixteen registers.
Shift/Serial Load— data present on the SI pin shifts into
the register on the falling edge of CP. Data enters the Q0
position and shifts toward Q15 on successive clocks, finally
appearing on the SO pin.
Parallel Load— data present on P0–P15 are entered into
the register on the falling edge of CP. The SO output repre-
sents the Q15 register output.
To prevent false clocking, CP must be LOW during a
LOW-to-HIGH transition of CS.
Block Diagram
Shift Register Operations Table
Control Input
CS
M
CP
H
X
X
L
L
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Transition
Operating Mode
Hold
Shift/Serial Load
Parallel Load
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