74HCT4538DB 查看數據表（PDF） - Philips Electronics

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74HCT4538DB

Dual retriggerable precision monostable multivibrator

Philips Electronics 

Philips Semiconductors

Dual retriggerable precision monostable

multivibrator

Product specification

74HC/HCT4538

FEATURES

• Separate reset inputs

• Triggering from leading or trailing edge

• Output capability: standard

• ICC category: MSI

• Power-on reset on-chip

GENERAL DESCRIPTION

The 74HC/HCT4538 are high-speed Si-gate CMOS

devices and are pin compatible with “4538” of the “4000B”

series. They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT4538 are dual retriggerable-resettable

monostable multivibrators. Each multivibrator has an

active LOW trigger/retrigger input (nA0), an active HIGH

trigger/retrigger input (nA1) , an overriding active LOW

direct reset input (nRD), an output (nQ) and its complement

(nQ), and two pins (nCTC and nRCTC) for connecting the

external timing components Ct and Rt. Typical pulse width

variation over temperature range is ± 0.2%.

The “4538” may be triggered by either the positive or the

negative edges of the input pulse. The duration and

accuracy of the output pulse are determined by the

external timing components Ct and Rt. The output pulse

width (T) is equal to 0.7 × Rt × Ct. The linear design

techniques guarantee precise control of the output pulse

width.

A LOW level at nRD terminates the output pulse

immediately.

Schmitt-trigger action in the trigger inputs makes the circuit

highly tolerant to slower rise and fall times.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

SYMBOL

PARAMETER

CONDITIONS

tPHL/ tPLH

CI

CPD

propagation delay nA0, nA1 to nQ, nQ

input capacitance

CL = 15 pF; VCC = 5 V

power dissipation capacitance per multivibrator notes 1 and 2

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) +

+ 0.48 × CEXT × VCC2 × fo + D × 0.8 × VCC where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

D = duty factor in %

CEXT = timing capacitance in pF

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

TYPICAL

HC

27

3.5

136

HCT

30

3.5

138

UNIT

ns

pF

pF

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

September 1993

2

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