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74LVC169 查看數據表(PDF) - NXP Semiconductors.

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74LVC169 Datasheet PDF : 24 Pages
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NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
PE
D0
D1
D2
D3
CP
U/D
CEP and CET
Q0
Q1
Q2
Q3
TC
13 14 15
012
22 1
load
count up
inhibit
Fig 7.
The following sequence is illustrated:
- Load (preset) to thirteen.
- Count up to fourteen, fifteen (maximum), zero, one and two.
- Inhibit.
- Count down to one, zero (minimum), fifteen, fourteen and thirteen.
Typical timing sequence
0 15 14 13
count down
001aaa648
74LVC169
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 29 November 2012
© NXP B.V. 2012. All rights reserved.
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