PCF85116-3T/01 查看數據表（PDF） - Philips Electronics
零件编号
产品描述 (功能)
生产厂家
PCF85116-3T/01 Datasheet PDF : 21 Pages
| |||
Philips Semiconductors
PCF85116-3
2048 × 8-bit CMOS EEPROM with I2C-bus interface
11. I2C-bus characteristics
Table 8: I2C-bus characteristics
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH
with an input voltage swing from VSS to VDD; see Figure 9.
Symbol Parameter
Conditions
Standard mode Fast mode
Unit
Min
Max
Min
Max
fSCL
clock frequency
tBUF
time the bus must be free before
new transmission can start
0
100
0
4.7
-
1.3
400 kHz
-
µs
tHD;STA
START condition hold time after
which first clock pulse is generated
4.0
-
0.6
-
µs
tLOW
LOW level clock period
4.7
-
1.3
tHIGH
HIGH level clock period
4.0
-
0.6
tSU;STA
set-up time for START condition
repeated start
4.7
-
0.6
tHD;DAT
data hold time
for CBUS compatible masters
5
-
-
-
µs
-
µs
-
µs
-
µs
for I2C-bus devices
[1] 0
-
0
-
ns
tSU;DAT
tr
tf
tSU;STO
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
250
-
100
-
ns
-
1000
20 + 0.1Cb[2] 300
µs
-
300
20 + 0.1Cb[2] 300
ns
4.0
-
0.6
-
µs
[1] The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
[2] Cb = total capacitance of one bus line in pF.
SDA
t BUF
t LOW
SCL
P
S
t HD;STA
tr
t HD;DAT
P = STOP condition; S = START condition.
Fig 9. Timing requirements for the I2C-bus.
tf
t HIGH
t SU;DAT
t HD;STA
S
t SU;STA
MBA705
P
t SU;STO
9397 750 14217
Product data
Rev. 04 — 25 October 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12 of 21
Share Link: 