SC515846 查看數據表（PDF） - Freescale Semiconductor
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SC515846 Datasheet PDF : 142 Pages
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Device User Guide — 9S12DT128DGV2/D V02.16
A.7.2 Slave Mode
Figure A-8 and Figure A-9 illustrate the slave mode timing. Timing values are shown in (Table A-19).
SS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT)
1
12
2
4
4
11
11 3
12
8
7
9
10
10
MISO
(OUTPUT)
SLAVE MSB OUT
BIT 6 . . . 1
SLAVE LSB OUT
MOSI
(INPUT)
5
6
MSB IN
BIT 6 . . . 1
LSB IN
Figure A-8 SPI Slave Timing (CPHA = 0)
SS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
1
2
12
4
4
11
9
SLAVE MSB OUT
7
5
6
MSB IN
10
BIT 6 . . . 1
BIT 6 . . . 1
3
11
12
8
SLAVE LSB OUT
LSB IN
Figure A-9 SPI Slave Timing (CPHA =1)
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