A32200A-1CQ256B 查看數據表（PDF） - Actel Corporation

零件编号

产品描述 (功能)

生产厂家

A32200A-1CQ256B

HiRel FPGAs

Actel Corporation 

can be combined with frequency and voltage to represent

active power dissipation.

Equivalent Capacitance

The power dissipated by a CMOS circuit can be expressed by

Equation 1:

Power (uW) = CEQ * VCC2 * F

(1)

where:

CEQ = Equivalent capacitance in pF

VCC = Power supply in volts (V)

F

= Switching frequency in MHz

Equivalent capacitance is calculated by measuring ICCactive

at a specified frequency and voltage for each circuit

component of interest. Measurements are made over a range

of frequencies at a fixed value of VCC. Equivalent capacitance

is frequency independent so that the results can be used over

a wide range of operating conditions. Equivalent capacitance

values are shown below.

CEQ Values for Actel FPGAs

1200XL

ACT 3 3200DX ACT 2 ACT 1

Modules (CEQM)

6.7 5.2 5.8 3.7

Input Buffers (CEQI)

7.2 11.6 12.9 22.1

Output Buffers (CEQO) 10.4 23.8 23.8 31.2

Routed Array Clock

Buffer Loads (CEQCR)

1.6 3.5 3.9 4.6

Dedicated Clock Buffer

Loads (CEQCD)

0.7 N/A N/A N/A

I/O Clock Buffer Loads

(CEQCI)

0.9 N/A N/A N/A

To calculate the active power dissipated from the complete

design, the switching frequency of each part of the logic must

be known. Equation 2 shows a piecewise linear summation

over all components that applies to all ACT 1, 1200XL,

3200DX, ACT 2, and ACT 3 devices. Since the ACT 1 family has

only one routed array clock, the terms labeled routed_Clk2,

dedicated_Clk, and IO_Clk do not apply. Similarly, the ACT 2

family has two routed array clocks, and the dedicated_Clk

and IO_Clk terms do not apply. For ACT 3 devices, all terms

will apply.

Power = VCC2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs +

(p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1

+ (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 +

(r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk +

(s2 * CEQCI * fs2)IO_Clk]

(2)

where:

m

n

p

q1

q2

r1

r2

s1

s2

CEQM

CEQI

CEQO

CEQCR

CEQCD

CEQCI

CL

fm

fn

fp

fq1

fq2

fs1

fs2

= Number of logic modules switching at fm

= Number of input buffers switching at fn

= Number of output buffers switching at fp

= Number of clock loads on the first routed

array clock (all families)

= Number of clock loads on the second routed

array clock (ACT 2, 1200XL, 3200DX, ACT 3

only)

= Fixed capacitance due to first routed array

clock (all families)

= Fixed capacitance due to second routed array

clock (ACT 2, 1200XL, 3200DX, ACT 3 only)

= Fixed number of clock loads on the dedicated

array clock (ACT 3 only)

= Fixed number of clock loads on the dedicated

I/O clock (ACT 3 only)

= Equivalent capacitance of logic modules in pF

= Equivalent capacitance of input buffers in pF

= Equivalent capacitance of output buffers

in pF

= Equivalent capacitance of routed array clock

in pF

= Equivalent capacitance of dedicated array

clock in pF

= Equivalent capacitance of dedicated I/O clock

in pF

= Output lead capacitance in pF

= Average logic module switching rate in MHz

= Average input buffer switching rate in MHz

= Average output buffer switching rate in MHz

= Average first routed array clock rate in MHz

(all families)

= Average second routed array clock rate in

MHz (ACT 2, 1200XL, 3200DX, ACT 3 only)

= Average dedicated array clock rate in MHz

(ACT 3 only)

= Average dedicated I/O clock rate in MHz

(ACT 3 only)

12

Share Link: