A32200A-1PG256C 查看數據表（PDF） - Actel Corporation

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A32200A-1PG256C

HiRel FPGAs

Actel Corporation 

Sequential Timing Characteristics (continued)

Flip-Flops and Latches (1200XL/3200DX, ACT 2, and ACT 1)

D

PRE

Y

E

CLK

CLR

(Positive edge triggered)

D1

G, CLK

E

Q

PRE, CLR

tSUD

tHD

tWCLKA

tSUENA

tHENA

tCO

Note:

1. D represents all data functions involving A, B, and S for multiplexed flip-flops.

tA

tRS

tWASYN

20

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