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A3977SLP 查看數據表(PDF) - Allegro MicroSystems

零件编号
产品描述 (功能)
生产厂家
A3977SLP
Allegro
Allegro MicroSystems Allegro
A3977SLP Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
3977
MICROSTEPPPING DMOS DRIVER
WITH TRANSLATOR
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise
noted)
Limits
Characteristic
Symbol
Test Conditions
Min. Typ.
Control Logic (cont’d)
Mixed Decay Trip Point
Ref. Input Voltage Range
Reference Input Current
Gain (Gm) Error
(note 3)
Crossover Dead Time
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
Logic Supply Current
PFDH
PFDL
VREF Operating
IREF
EG VREF = 2 V, Phase Current = 38.27%
VREF = 2 V, Phase Current = 70.71%
VREF = 2 V, Phase Current = 100.00%
tDT SR enabled
TJ
TJ
VUVLO Increasing VDD
VUVLO
IDD fPWM < 50 kHz
Outputs off
0
100
2.45
0.05
0.6VDD
0.21VDD
0
475
165
15
2.7
0.10
Sleep mode
* Operation at a step frequency greater than the specied minimum value is possible but not warranteed.
NOTES: 1. Typical Data is for design information only.
2. Negative current is dened as coming out of (sourcing) the specied device terminal.
3. EG = ([VREF/8] – VSENSE)/(VREF/8)
Max.
VDD
±3.0
±10
±5.0
±5.0
800
2.95
12
10
20
Units
V
V
V
µA
%
%
%
ns
°C
°C
V
V
mA
mA
µA
www.allegromicro.com
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