A3987 查看數據表（PDF） - Allegro MicroSystems

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A3987

DMOS Microstepping Driver with Translator

Allegro MicroSystems 

A3987

DMOS Microstepping Driver with Translator

the internal body diodes, and switching transients related to the

capacitance of the load. The blank time, tBLANK , is internally set

to approximately 1 μs.

Charge Pump (CP1 and CP2) The charge pump is used to

generate a gate supply greater than VBBx to drive the source FET

gates. A 0.1 μF ceramic capacitor is required between CP1 and

CP2 for pumping purposes. A 0.1μF ceramic capacitor is required

between VCP and the VBB terminals to act as a reservoir to oper-

ate the high-side FETs.

Internal Regulator (VREG) The VREG terminal should

be decoupled with a 0.22 μF capacitor to ground. This internally

generated voltage is used to operate the sink FET outputs. VREG

is internally monitored, and in the case of a fault condition, the

outputs of the device are disabled.

Enable Input (ENABLE) This input activates all of the FET

outputs. When logic high, the outputs are disabled, and when

logic low, the outputs are enabled. Inputs to the translator (STEP,

DIR, MS1, and MS2) are always active, except in Sleep mode,

regardless of the ENABLE input state.

Shutdown In the event of a fault (either excessive junction

temperature, or low voltage on VCP), the outputs of the device

are disabled until the fault condition is removed. At power-up,

the undervoltage lockout (UVLO) circuit disables the drivers and

resets the translator to the home state.

Mixed Decay Operation The full bridges can operate in

mixed decay mode when set by the step sequence (see figures 3

through 5). As the trip point is reached, the device goes into fast

decay mode for 30.1% of the fixed off-time, tOFF. After this fast

decay portion, tFD , the device switches to slow decay mode for

the remainder of the fixed off-time period.

Synchronous Rectification When a PWM off-cycle is

triggered by an internal fixed off-time cycle, load current will

recirculate according to the decay mode selected by the control

logic. The A3987 synchronous rectification feature turns on the

appropriate FETs during current decay, effectively shorting out

the body diodes in the low RDS(on) driver. This lowers power

dissipation significantly, and can eliminate the need for external

Schottky diodes for many applications. To prevent reversal of

load current, synchronous rectification is turned off when a zero

current level is detected.

Short-to-Ground Should a motor winding short to ground,

the current through the short will rise until the overcurrent thresh-

old, ICOPST , a minimum of 2 A, is exceeded. The driver turns off

after a short propagation delay and latches the fault. The device

will remain disabled until the SLEEP/RESET input goes high or

VDD power is removed. As shown in figure 6, a short-to-ground

produces a single overcurrent event.

Shorted Load During a shorted load event, the current path is

through the sense resistor. During this fault condition the device

will be protected, however, the fault will not be latched. When

the full bridge turns on, the current will rise and exceed the over-

current threshold. After the blank time,tBLANK , of approximatly

1 μs, the driver will look at the voltage on the SENSEx pin. The

voltage on the SENSEx pin will be larger than the voltage set by

the REF pin, and the full bridge will turn off for the time set by

the ROSC pin. Figure 7 shows a shorted load condition with an

off-time of 30 μs.

Fault latched

toff = 30 μs

2 A / div.

500 ns / div.

Figure 6. Short-to-ground event

2 A / div.

5 μs / div.

Figure 7. Short-to-load event

Allegro MicroSystems, Inc.

10

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

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