A3987 查看數據表（PDF） - Allegro MicroSystems

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A3987

DMOS Microstepping Driver with Translator

Allegro MicroSystems 

A3987

DMOS Microstepping Driver with Translator

Functional Description

Device Operation The A3987 is a complete microstepping

motor driver with built-in translator for easy operation with

a minimum of control lines. The A3987 is designed to oper-

ate bipolar stepper motors in full, half, quarter, and sixteenth

step modes. The full bridges on the dual outputs are composed

entirely of N-channel DMOS FETS, and the full bridge currents

are regulated by fixed off-time, pulse width modulated (PWM)

control circuitry. For each full bridge, the individual step currents

are set by the combination of: a common external reference volt-

age, VREF ; an external current sense resistor, RSENSEx ; and the

output voltage of an internal DAC that is controlled by the output

of the translator.

At power-up or reset, the translator sets the DACs and phase

current polarity to the initial home state (see figures 2 through

5 for home state conditions), and also sets the current regulator

for both output phases to mixed decay mode. When a command

signal occurs on the STEP input, the translator automatically

sequences the DACs to the next level (see table 2 for the current

level sequence) and current polarity. The microstep resolution

is set by inputs MS1 and MS2 (see in table 1 for state settings).

If logic inputs are pulled up to VDD, it is good practice to use a

high value pull-up resistor in order to limit current to the logic

inputs should an overvoltage event occur. If the new DAC output

level is lower than the previous level, then the decay mode for

that full bridge will be set to mixed decay. If the new DAC level

is higher or equal to the previous level, then the decay mode for

that full bridge will be slow decay. This automatic current decay

selection improves microstepping performance by reducing the

distortion of the current waveform due to the motor BEMF.

Low-Power Mode Select (SLEEP/RESET) An active-

low control input used to minimize power consumption when the

A3987 is not in use. This disables much of the internal circuitry

including the output FETs and internal regulator. A logic high

allows normal device operation and power-up in the home state.

When coming out of sleep mode, a 1 ms delay is required before

issuing a STEP command, to allow the internal regulator to

stabilize. The outputs can also be reset to the home state without

entering sleep mode. To do so, pulse this input low for a duration

between tRP(min) and tRP(max).

Step Input (STEP) A low-to-high transition on the STEP

input sequences the translator and advances the motor one incre-

ment. The translator controls the input to the DACs and the direc-

tion of current flow in each winding. The size of the increment is

determined by the state of inputs MS1 and MS2.

Microstep Select (MS1 and MS2) Inputs MS1 and MS2

select the microstepping format (see table 1 for state settings).

Changes to these inputs do not take effect until the next STEP

command. It is good practice to use a pull-up resistor to VDD in

order to limit input current should an external overvoltage occur.

A minimum of 5 kΩ is recommended.

Direction Input (DIR) The state of the DIR input determines

the direction of rotation of the motor. A logic change on the DIR

pin will not take effect until the next STEP command is issued.

Internal PWM Current Control Each full bridge is

controlled by a fixed off-time PWM current control circuit that

limits the load current to a desired value (ITRIP). Initially, a

diagonal pair of source and sink FETs are enabled and current

flows through the motor winding and the corresponding current

sense resistor, RSENSEx. When the voltage across RSENSE equals

the DAC output voltage, the current sense comparator resets the

PWM latch, which turns off the source drivers (in slow decay

mode) or the sink and source drivers (in fast or mixed decay

modes).

The maximum value of current limiting is set by the selection of

RSENSE and the voltage at the REF input, with a transconductance

function approximated by:

ITRIP(max) = VREF / 8 × RSENSE .

The DAC output reduces the VREF output to the current sense

comparator in precise steps:

ITRIP = (% ITRIP(max) / 100) × ITRIP(max) ,

(see table 2 for % ITRIP(max) at each step).

Note: It is critical that the absolute maximum voltage rating

(0.5 V) on the SENSE pins is not exceeded.

Fixed Off-Time The internal PWM current control circuitry

uses a 4 MHz master oscillator to control the duration of time that

the drivers remain off. The fixed off-time, tOFF , is determined by

the selection of an external resistor connected from the ROSC

timing terminal to VDD. If the ROSC terminal is tied directly to

GND, tOFF defaults to 25 μs. The off-time is approximated by:

tOFF ≈ ROSC / 1.981 × 109

The master oscillator period is used to derive PWM off-time,

dead time, and blanking time.

Blanking This function blanks the output of the current sense

comparator when the outputs are switched by the internal current

control circuitry. The comparator output is blanked to prevent

false overcurrent detections due to reverse recovery currents of

Allegro MicroSystems, Inc.

9

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

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