A64S06162AG 查看數據表（PDF） - AMIC Technology

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A64S06162AG

16M(1M x 16bit) Normal mode & Page mode with Deep Power Down Static Random Access Memory

AMIC Technology 

Preliminary

TIMING DIAGRAMS

READ CYCLE (/PD = /WE = VIH)

tRC

Address(A2 – A19)

Page Address(A0 – A1)

/CS

tAS

/UB,/LB

/OE

tAA

tCO

tLZ(2)

tBA

tOE

DATA OUT

A64S06162A

tP

tHZ(1,2)

tOHZ(1)

Note (READ CYCLE) :

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are

not referenced to output voltage levels

2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given

device and from device to device.

3. /WE is high for the read cycle.

4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us.

(May, 2005, Version 0.0)

8

AMIC Technology, Corp.

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