A8504EECTR-T 查看數據表（PDF） - Allegro MicroSystems
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A8504EECTR-T Datasheet PDF : 18 Pages
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A8504
WLED/RGB Backlight Driver for Medium Size LCDs
PCB Layout Guidelines
The A8504 evaluation board provides a useful model for design-
ing application circuit layouts. The following guidelines should
be observed:
• Place the supply bypass capacitor, C8, close to the VIN pin and
the ground plane.
• Route analog ground, digital signal ground, LED ground
(LGND pin), and power ground (PGND pin) separately. Con-
nect all these grounds at the pad for the exposed thermal pad
under the A8504, serving as a star ground.
• Place the input capacitors, C2 and C7, the inductor, L1, the
boost diode D1, and the internal MOSFET and output capaci-
tor, C4, so that they form the smallest loop practical. Avoid
long traces for these paths.
• Place the RISET, RFSET, and OVP resistors and the compensa-
tion capacitor, C5, close to the ISET, FSET, OVP, and COMP
pins, respectively.
• Provide a substantial solder pad under the exposed thermal
pad on the bottom side of the A8504, to provide good thermal
conduction. Connect the PCB solder pad to the PCB ground
plane with multiple thermal vias. For a thermal via specifica-
tion, please refer to JEDEC guidelines.
• For best thermal performance, avoid thermal stresses.
VIN
GND
L1
VBAT
CBAT
COUT
CIN
D1
VOUT
ROVP
CC
RFSET RISET
1
PGND
PAD
2
SKIP
3
COMP
4
FSET
5
ISET
A8504
6
GND
7
LED1
21
PGND
20
PWM
GND 19
18
SEL3
17
SEL2
16
SEL1
15
LED2
RPWM
Figure 13. Schematic diagram of A8504 typical application circuit and composite view of typical PCB
layout. In the composite view, the red line superimposed represents the current loop during switch
on-time (return through the A8504 device and the PCB ground plane). The green line represents the
current loop during off-time. Both of these loops should be designed to be as short as practicable.
Allegro MicroSystems, Inc.
15
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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