5962-9755701HPC 查看數據表（PDF） - Avago Technologies
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5962-9755701HPC Datasheet PDF : 16 Pages
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Applications Information
Functional Description
Figure 23 shows the primary functional blocks of the
HCPL-7850. In operation, the sigma-delta modulator
converts the analog input signal into a high-speed serial
bit stream. The time average of this bit stream is directly
proportional to the input signal. This stream of digital
data is encoded and optically transmitted to the detector
circuit. The detected signal is decoded and converted
back into an analog signal, which is filtered to obtain the
final output signal.
Application Circuit
The recommended application circuit is shown in Figure
24. A floating power supply (which in many applica-
tions could be the same supply that is used to drive the
high-side power transistor) is regulated to 5 V using a
simple three-terminal voltage regulator (U1). The voltage
from the current sensing resistor, or shunt (Rsense), is
applied to the input of the HCPL-7850 through an RC
anti-aliasing filter (R5, C3). And finally, the differential
output of the isolation amplifier is converted to a ground-
referenced single-ended output voltage with a simple
differential amplifier circuit (U3 and associated com-
ponents). Although the application circuit is relatively
simple, a few recommendations should be followed to
ensure optimal performance.
1
2
U2
3
4
HCPL-7850
C5
150 pF
+5 V
R3
+5 V
8 C4
R4A
20.0 K
0.1 PF
7
R1
10.0 K
6
R2
10.0 K
10.0 K
+5 V
C8
0.1 PF
–
U3
+ MC34071
5
C6
150 pF
R4B
20.0 K
Supplies and Bypassing
As mentioned above, an inexpensive three-terminal
regulator can be used to reduce the gate-drive power
supply voltage to 5 V. To help attenuate high frequency
power supply noise or ripple, a resistor or inductor can
be used in series with the input of the regulator to form a
low-pass filter with the regulator’s input bypass capacitor.
As shown in Figure 24, a 0.1 F bypass capacitor (C2, C4)
should be located as close as possible to the input and
output power supply pins of the HCPL-7850. The bypass
capacitors are required because of the high-speed digital
nature of the signals inside the isolation amplifier. A 0.01
F bypass capacitor (C3) is also recommended at the
input pin(s) due to the switched-capacitor nature of the
input circuit. The input bypass capacitor should be at least
1000 pF to maintain gain accuracy of the isolation amplifier.
Inductive coupling between the input power-supply
capacitor and the input circuit, including the input
bypass capacitor and the input leads of the HCPL-7850,
can introduce additional DC offset in the circuit. Several
steps can be taken to minimize the mutual coupling
between the two parts of the circuit, thereby improving
the offset performance of the design. Separate the two
bypass capacitors C2 and C3 as much as possible (even
putting them on opposite sides of the PC board), while
keeping the total lead lengths, including traces, of each
bypass capacitor less than 20 mm. PC board traces should
be made as short as possible and placed close together
or over ground plane to minimize loop area and pickup
of stray magnetic fields. Avoid using sockets, as they will
typically increase both loop area and inductance. And
finally, using capacitors with small body size and orienting
them perpendicular to each other on the PC board can
also help. For more information concerning this effect, see
Application Note 1078, Designing with Avago Technolo-
gies Isolation Amplifiers.
VOUT
Figure 25. Single-Supply Post-Amplifier Circuit.
R5
C2 C4
C3
Figure 26. Top Layer of Printed Circuit Board Layout.
13
TO VDD1
TO RSENSE+
TO RSENSE–
TO VDD2
VOUT+
VOUT–
Figure 27. Bottom Layer of a Printed Circuit Board Layout.
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