ACPL-M75L 查看數據表（PDF） - Avago Technologies

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ACPL-M75L

Single-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature

Avago Technologies 

CMR with Other Drive Circuits

CMR performance with drive circuits other than that

shown in Figure 13 may be enhanced by following these

guidelines:

1. Use of drive circuits where current is shunted from the

LED in the LED “off” state (as shown in Figures 15 and

16). This is beneficial for good CMH.

2. Use of typical IFH = 6mA per datasheet recommendation

Using any one of the drive circuits in Figures 15-17 with

IF = 6 mA will result in a typical CMR of 10 kV/μs for ACPL-

M75L, as long as the PC board layout practices are fol-

lowed. Figure 15 shows a circuit which can be used with

any totem-pole-output TTL/LSTTL/HCMOS logic gate. The

buffer PNP transistor allows the circuit to be used with

logic devices which have low current-sinking capability.

It also helps maintain the driving-gate power-supply cur-

rent at a constant level to minimize ground shifting for

other devices connected to the input-supply ground.

When using an open-collector TTL or open-drain CMOS

logic gate, the circuit in Figure 16 may be used. When

using a CMOS gate to drive the optocoupler, the circuit

shown in Figure 17, where the resistor is recommended to

connect to the anode of the LED, may be used.

V DD1

74LS04 OR ANY TOTEM-

POLE OUTPUT LOGIC GATE

GND 1

Rtotal = 300Ω-for VDD =3.3V

= 580Ω-for VDD =5V

1/2R total

V DD2

1/2R total

VO

0.1μF

SHIELD

GND 2

Figure 13. Recommended drive circuit for ACPL-M75L for high-CMR

½ R total

½ R total

ILP

C LA

ILN CLC

SHIELD

VDD2

0.1μF

VO

15pF

GND 2

74L504

(ANY

TTL/CMOS

GATE)

VDD

530 Ω

ACPL-M75L

2N3906

(ANY PNP)

1

LED

3

Figure 14. AC equivalent of ACPL-M75L

Figure 15. TTL interface circuit for the ACPl-M75L families.

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