ACPL-W314-000E(2009) 查看數據表（PDF） - Avago Technologies
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ACPL-W314-000E Datasheet PDF : 13 Pages
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LED Drive Circuit Considerations for Ultra High CMR Per-
formance
Without a detector shield, the dominant cause of opto-
coupler CMR failure is capacitive coupling from the input
side of the optocoupler, through the package, to the
detector IC as shown in Figure 21. The ACPL-P314/W314
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts the
capacitively coupled current away from the sensitive IC
circuitry. However, this shield does not eliminate the ca-
pacitive coupling between the LED and optocoupler pins
5-8 as shown in Figure 22. This capacitive coupling causes
perturbations in the LED current during common mode
transients and becomes the major source of CMR failures
for a shielded optocoupler. The main design objective of
a high CMR LED drive circuit becomes keeping the LED in
the proper state (on or off ) during common mode tran-
sients. For example, the recommended application circuit
(Figure 19), can achieve 10 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in the proper state are
discussed in the next two sections.
1
CLEDP
6
2
5
3
CLEDN
4
Figure 21. Optocoupler Input to Output Capacitance Model for Unshielded
Optocouplers.
1
CLEDP CLED01
6
2
CLED02
5
3
CLEDN
SHIELD
4
Figure 22. Optocoupler Input to Output Capacitance Model for Shielded
Optocouplers.
CMR with the LED On (CMRH)
A high CMR LED drive circuit must keep the LED on
during common mode transients. This is achieved by
overdriving the LED current beyond the input threshold
so that it is not pulled below the threshold during a
transient. A minimum LED current of 8 mA provides
adequate margin over the maximum IFLH of 5 mA to
achieve 10 kV/µs CMR.
CMR with the LED Off (CMRL)
A high CMR LED drive circuit must keep the LED off (VF
≤ VF(OFF)) during common mode transients. For example,
during a -dVCM/dt transient in Figure 23, the current
flowing through CLEDP also flows through the RSAT and
VSAT of the logic gate. As long as the low state voltage
developed across the logic gate is less than VF(OFF) the
LED will remain off and no common mode failure will
occur.
+5 V
+
VSAT
-
1
CLEDP
ILEDP
2
6
0.1 µF
5
3
CLEDN
SHIELD
4
• THEARROWS INDICATETHEDIRECTION
• OF CURRENTFLOW DURING - dVCM/ dt
+VCC = 18V
-
Rg
VCM
+5 V
+
VSAT
-
1
CLEDP
ILEDP
2
6
0.1 µF
5
3
CLEDN
SHIELD
4
• THE ARROWS INDICATE THE DIRECTION
• OF CURRENT FLOW DURING - dVCM/dt
+ VCC = 18V
- Rg
VCM
Figure 23. Equivalent Circuit for Figure 17 During Common Mode Transient.
The open collector drive circuit, shown in Figure 24, can
not keep the LED off during a +dVCM/dt transient, since
all the current flowing through CLEDN must be supplied
by the LED, and it is not recommended for applications
requiring ultra high CMR1 performance. The alternative
drive circuit which like the recommended application
circuit (Figure 19), does achieve ultra high CMR perfor-
mance by shunting the LED in the off state.
+5 V
1
CLEDP
6
2
5
CLEDN
3 ILEDN
SHIELD
4
Q1
Figure 24. Not Recommended Open Collector Drive Circuit.
12
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