AD1835A(Rev0) 查看數據表（PDF） - Analog Devices

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AD1835A
(Rev.:Rev0)

2 ADC, 8 DAC, 96 kHz, 24-Bit Σ-Δ Codecs

Analog Devices 

AD1835A

Pin Name

ASDATA (O)

DSDATA1 (I)

DSDATA2 (I)/AAUXDATA1 (I)

DSDATA3 (I)/AAUXDATA2 (I)

DSDATA4 (I)/AAUXDATA3 (I)

ALRCLK (O)

ABCLK (O)

DLRCLK (I)/AUXLRCLK(I/O)

DBCLK (I)/AUXBCLK(I/O)

Table II. Pin Function Changes in Auxiliary Mode

I2S Mode

I2S Data Out, Internal ADC

I2S Data In, Internal DAC1

I2S Data In, Internal DAC2

I2S Data In, Internal DAC3

I2S Data In, Internal DAC4

LRCLK for ADC

BCLK for ADC

LRCLK In/Out Internal DACs

BCLK In/Out Internal DACs

Aux Mode

TDM Data Out to SHARC.

TDM Data In from SHARC.

AUX-I2S Data In 1 (from external ADC).

AUX-I2S Data In 2 (from external ADC).

AUX-I2S Data In 3 (from external ADC).

TDM Frame Sync Out to SHARC (FSTDM).

TDM BCLK Out to SHARC.

AUX LRCLK In/Out. Driven by external LRCLK from ADC in

slave mode. In master mode, driven by MCLK/512.

AUX BCLK In/Out. Driven by external BCLK from ADC

in slave mode. In master mode, driven by MCLK/8.

FSTDM

BCLK

TDM

ASDATA1

TDM (OUT)

ASDATA

DSDATA1

TDM (IN)

DSDATA1

MSB TDM

1ST

CH

MSB TDM

8TH

CH

INTERNAL

ADC L1

32

MSB TDM

1ST

CH

AUX_ADC L2 AUX_ADC L3 AUX_ADC L4

INTERNAL

ADC R1

AUX_ADC R2 AUX_ADC R3 AUX_ADC R4

MSB TDM

8TH

CH

INTERNAL

DAC L1

32

INTERNAL

DAC L2

INTERNAL

DAC L3

INTERNAL

DAC L4

INTERNAL

DAC R1

INTERNAL

DAC R2

INTERNAL

DAC R3

INTERNAL

DAC R4

AUX

LRCLK I2S

(FROM AUX ADC#1)

AUX

BCLK I2S

(FROM AUX ADC#1)

AAUXDATA1 (IN)

(FROM AUX ADC#1)

AAUXDATA2 (IN)

(FROM AUX ADC#2)

LEFT

I2S – MSB LEFT

I2S – MSB LEFT

RIGHT

I2S – MSB RIGHT

I2S – MSB RIGHT

AAUXDATA3 (IN)

(FROM AUX ADC #3)

I2S – MSB LEFT

AUX BCLK FREQUENCY IS 64 ؋ FRAME RATE; TDM BCLK FREQUENCY IS 256 ؋ FRAME RATE.

Figure 11. Aux Mode Timing

I2S – MSB RIGHT

–16–

REV. 0

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