AD1849KP 查看數據表（PDF） - Analog Devices
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AD1849KP Datasheet PDF : 28 Pages
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DIGITAL TIMING PARAMETERS (Guaranteed over 4.75 V to 5.25 V, 0؇C to 70؇C)
Min
Typ
SCLK Period (tCLK)
Slave Mode, MS = 0
Master Mode, MS = 1*
SCLK HI (tHI)*
Slave Mode, MS = 0
SCLK LO (tLO)*
Slave Mode, MS = 0
CLKIN Frequency
CLKIN HI
CLKIN LO
Crystals Frequency
Input Setup Time (tS)
Input Hold Time (tIH)
Output Delay (tD)
Output Hold Time (tOH)
Output Hi-Z to Valid (tZV)
Output Valid to Hi-Z (tVZ)
Power Up RESET LO Time
Operating RESET LO Time
80
1/(FS × Bits per Frame)
25
25
30
30
15
10
0
15
50
100
POWER SUPPLY
Power Supply Voltage Range*
–Digital and Analog
Power Supply Current—Operating
(50% IVDD, 50% IVCC, Unloaded Outputs)
Power Supply Current—Power Down
Power Supply Rejection (@ 1 kHz)*
(At Both Analog and Digital
Supply Pins, Both ADCs and DACs)
Min
Typ
4.75
100
20
40
CLOCK SPECIFICATIONS*
Input Clock Frequency, Crystals
Clock Duty Cycle Tolerance
Sample Rate (FS)
*Guaranteed, not tested.
Specifications subject to change without notice.
Min
5.5125
Max
13.5
27
25
20
Max
5.25
130
200
Max
27
± 10
50
AD1849K
Unit
ns
s
ns
ns
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ms
ns
Unit
V
mA
µA
dB
Unit
MHz
%
kHz
REV. A
–5–
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