AD5441 查看數據表（PDF） - Analog Devices

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AD5441

12-Bit Serial Input Multiplying DAC

Analog Devices 

AD5441

BIPOLAR 4-QUADRANT MULTIPLYING

Figure 22 shows a suggested circuit to achieve 4-quadrant

multiplying operation. The summing amplifier multiplies VOUT1

by 2 and offsets the output with the reference voltage so that a

midscale digital input code of 2048 places VOUT2 at 0 V. The

negative full-scale voltage will be VREF when the DAC is loaded

with all zeros. The positive full-scale output will be −(VREF − 1

LSB) when the DAC is loaded with all ones. Therefore, the

digital coding is offset binary. The voltage output transfer

equation for various input data and reference (or signal) values

follows

VOUT2 = (D/2048 − 1) − VREF

where:

D is the decimal data loaded into the DAC register.

VREF is the externally applied reference voltage source.

R3

20kΩ

VDD

R2

R5

20kΩ

VREF

± 10V

VDD

RFB

VREF AD5441

R1

IOUT1

GND

LD CLK SRI

C1

A1

R4

10kΩ

A2

VOUT = –VREF TO +VREF

AGND

μCONTROLLER

NOTES

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.

2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS

R3 AND R4.

3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED

IF A1/A2 IS A HIGH SPEED AMPLIFIER.

Figure 22. Bipolar (4-Quadrant) Operation

Preliminary Technical Data

INTERFACE LOGIC INFORMATION

The AD5441 has been designed for ease of operation. The

timing diagram in Figure 5 illustrates the input register loading

sequence. Note that the most significant bit (MSB) is loaded

first. Once the 12-bit input register is full, the data is transferred

to the DAC register by taking LD momentarily low.

DIGITAL SECTION

The AD5441’s digital inputs, SRI, LD, and CLK, are TTL

compatible. The input voltage levels affect the amount of

current drawn from the supply; peak supply current occurs as

the digital input (VIN) passes through the transition region. See

Figure 8 for the supply current vs. logic input voltage graph.

Maintaining the digital input voltage levels as close as possible

to the supplies, VDD and GND, minimizes supply current

consumption. The AD5441’s digital inputs have been designed

with ESD resistance incorporated through careful layout and

the inclusion of input protection circuitry. Figure 23 shows the

input protection diodes and series resistor; this input structure

is duplicated on each digital input. High voltage static charges

applied to the inputs are shunted to the supply and ground rails

through forward-biased diodes. These protection diodes were

designed to clamp the inputs to well below dangerous levels

during static discharge conditions.

VDD

5kΩ

LD, CLK, SRI

GND

Figure 23. Digital Input Protection

Rev. PrA | Page 12 of 16

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