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AD5441 查看數據表(PDF) - Analog Devices

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AD5441 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5441
VREF 1
RFB 2
IOUT 3
GND 4
AD5441
TOP VIEW
(Not to Scale)
8 VDD
7 CLK
5 SRI
5 LD
Figure 3. 8-LeadLFCSP Pin Configuration
VREF 1
8 VDD
RFB 2 AD5441 7 CLK
IOUT 3 TOP VIEW 6 SRI
GND 4 (Not to Scale) 5 LD
Figure 4. 8-Lead MSOP Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Descriptions
1
VREF
DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.
2
RFB
Internal Matching Feedback Resistor. Connect to external op amp output.
3
IOUT
DAC Current Output, full-scale output 1 LSB less than reference input voltage −VREF.
4
GND
Analog and Digital Ground.
5
LD
Load Strobe, Level-Sensitive Digital Input. Transfers shift-register data to DAC register while active low.
See Table 4 for operation.
6
SRI
12-Bit Serial Register Input, data loads directly into the shift register MSB first. Extra leading bits are ignored.
7
CLK
Clock Input, positive-edge clocks data into shift register.
8
VDD
Positive Power Supply Input. Specified range of operation 5 V ± 10%.
Rev. PrA | Page 5 of 16

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