AD5678BRUZ-2REEL7 查看數據表（PDF） - Analog Devices

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AD5678BRUZ-2REEL7

4 × 12-Bit and 4 × 16-Bit Octal DAC with On-Chip Reference in 14-Lead TSSOP

Analog Devices 

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on

its output, which gives an output range of 0 V to VDD. The

amplifier is capable of driving a load of 2 kΩ in parallel with

1,000 pF to GND. The source and sink capabilities of the output

amplifier can be seen in Figure 24 and Figure 25. The slew rate

is 1.5 V/μs with a ¼ to ¾ scale settling time of 10 μs.

SERIAL INTERFACE

The AD5678 has a 3-wire serial interface (SYNC, SCLK, and

DIN) that is compatible with SPI, QSPI, and MICROWIRE

interface standards as well as most DSPs. See Figure 2 for a

timing diagram of a typical write sequence.

The write sequence begins by bringing the SYNC line low. Data

from the DIN line is clocked into the 32-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 50 MHz, making the AD5678 compatible with high speed

DSPs. On the 32nd falling clock edge, the last data bit is clocked

in and the programmed function is executed, that is, a change

in DAC register contents and/or a change in the mode of

operation. At this stage, the SYNC line can be kept low or be

brought high. In either case, it must be brought high for a

minimum of 15 ns before the next write sequence so that a

falling edge of SYNC can initiate the next write sequence.

Because the SYNC buffer draws more current when VIN = 2 V

than it does when VIN = 0.8 V, SYNC should be idled low

between write sequences for even lower power operation of the

part. As is mentioned previously, however, SYNC must be

brought high again just before the next write sequence.

AD5678

Table 7. Command Definitions

Command

C3 C2 C1 C0 Description

0 0 0 0 Write to Input Register n

0 0 0 1 Update DAC Register n

0 0 1 0 Write to Input Register n, update all

(software LDAC)

0 0 1 1 Write to and update DAC Channel n

0 1 0 0 Power down/power up DAC

0 1 0 1 Load clear code register

0 1 1 0 Load LDAC register

0 1 1 1 Reset (power-on reset)

1 0 0 0 Set up internal REF register

1 0 0 1 Reserved

– – – – Reserved

1 1 1 1 Reserved

Table 8. Address Commands

Address (n)

A3

A2

A1

A0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

1

1

1

Selected DAC

Channel

DAC A (16 bits)

DAC B (16 bits)

DAC C (12 bits)

DAC D (12 bits)

DAC E (12 bits)

DAC F (12 bits)

DAC G (16 bits)

DAC H (16 bits)

All DACs

Rev. C | Page 21 of 28

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