AD5821AD-WAFER 查看數據表（PDF） - Analog Devices

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AD5821AD-WAFER

120 mA, Current Sinking, 10-Bit, I2C DAC

Analog Devices 

AD5821A

THEORY OF OPERATION

The AD5821A is a fully integrated, 10-bit DAC with 120 mA

output current sink capability. It is intended for driving voice

coil actuators in applications such as lens autofocus, image

stabilization, and optical zoom. The circuit diagram is shown in

Figure 20. A 10-bit current output DAC coupled with Resistor R

generates the voltage that drives the noninverting input of the

operational amplifier. This voltage also appears across the RSENSE

resistor and generates the sink current required to drive the

voice coil.

Resistor R and Resistor RSENSE are interleaved and matched.

Therefore, the temperature coefficient and any nonlinearities

over temperature are matched, and the output drift over tempera-

ture is minimized. Diode D1 is an output protection diode.

XSHUTDOWN

VDD

DGND

SDA

SCL

REFERENCE

POWER-ON

RESET

I2C SERIAL

INTERFACE

10-BIT

CURRENT

OUTPUT DAC

VDD

D1

ISINK

R

AD5821A

RSENSE

3.3Ω

DGND

AGND

Figure 20. Block Diagram Showing Connection to Voice Coil

SERIAL INTERFACE

The AD5821A is controlled using the industry-standard I2C

2-wire serial protocol. Data can be written to or read from the

DAC at data rates of up to 400 kHz. After a read operation, the

contents of the input register are reset to all 0s.

I2C BUS OPERATION

An I2C bus operates with one or more master devices that

generate the serial clock (SCL) and read and write data on

the serial data line (SDA) to and from slave devices such as

the AD5821A. On all devices on an I2C bus, the SDA pin is

connected to the SDA line and the SCL pin connected to the

SCL line of the master device. I2C devices can only pull the bus

lines low; pulling high is achieved by pull-up resistors, RP. The

value of RP depends on the data rate, bus capacitance, and the

maximum load current that the I2C device can sink (3 mA for a

standard device).

1.8V

RP RP

SDA

SCL

When the bus is idle, SCL and SDA are both high. The master

device initiates a serial bus operation by generating a start

condition, which is defined as a high-to-low transition on the

SDA low while SCL is high. The slave device connected to the

bus responds to the start condition and shifts in the next eight

data bits under control of the serial clock.

These eight data bits consist of a 7-bit address, plus a read/write

(R/W) bit that is 0 if data is to be written to a device, and 1 if

data is to be read from a device. Each slave device on an I2C bus

must have a unique address. The address of the AD5821A is

0001100; however, 0001101, 0001110, and 0001111 address the

part because the last two bits are unused/don’t cares (see Figure 22

and Figure 23). Because the address plus the R/W bit always

equals eight bits of data, the write address of the AD5821A is

00011000 (0x18) and the read address is 00011001 (0x19) (see

Figure 22 and Figure 23).

At the end of the address data, after the R/W bit, the slave

device that recognizes its own address responds by generating

an acknowledge (ACK) condition. This is defined as the slave

device pulling SDA low while SCL is low before the ninth clock

pulse and keeping it low during the ninth clock pulse. Upon

receiving the ACK, the master device can clock data into the

AD5821A in a write operation, or it can clock it out in a read

operation. Data must change either during the low period of the

clock (because SDA transitions during the high period define a

start condition), or during a stop condition, as described in the

Data Format section.

I2C data is divided into blocks of eight bits, and the slave generates

an ACK at the end of each block. Because the AD5821A requires

10 bits of data, two data-words must be written to it when a

write operation occurs, or read from it when a read operation

occurs. At the end of a read or write operation, the AD5821A

acknowledges the second data byte. The master generates a stop

condition, defined as a low-to-high transition on SDA while SCL

is high, to end the transaction.

DATA FORMAT

Data is written to the AD5821A high byte first, MSB first, and is

shifted into the 16-bit input register. After all data is shifted in,

data from the input register is transferred to the DAC register.

Because the DAC requires only 10 bits of data, not all bits of the

input register data are used. The MSB is reserved for an active-

high, software-controlled, power-down function.

The data format is shown in Table 6. When referring to this table,

note that Bit 14 is unused; Bit 13 to Bit 4 correspond to the DAC

data bits, D9 to D0; and Bit 3 to Bit 0 are unused.

During a read operation, data is read in the same bit order.

I2C MASTER

DEVICE

I2C SLAVE

DEVICE

AD5821 A

Figure 21. Typical I2C Bus

I2C SLAVE

DEVICE

Rev. 0 | Page 11 of 16

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