AD627(RevA) 查看數據表（PDF） - Analog Devices
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AD627
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
AD627 Datasheet PDF : 16 Pages
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AD627
2 V or 1 V to maximize the available gain and output swing.
Note that in most cases, there is no advantage to increasing the
single supply to greater than 5 V (the exception being an input
range of 0 V to 1 V).
5
4
3
2
MAXIMUM VREF
1
0
–1
MINIMUM VREF
–2
–3
–4
–5
–6 –5 –4 –3 –2 –1 0 1 2 3 4
VIN(–) – Volts
Figure 35. Reference Input Voltage vs. Negative Input
Voltage, VS = ±5 V, G = 5
5
MAXIMUM VREF
4
3
2
MINIMUM VREF
1
0
–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
VIN(–) – Volts
Figure 36. Reference Input Voltage vs. Negative Input
Voltage, VS = +5 V, G = 5
Output Buffering
The AD627 is designed to drive loads of 20 kΩ or greater but
can deliver up to 20 mA to heavier loads at lower output voltage
swings (see Figure 7). If more than 20 mA of output current is
required at the output, the AD627’s output should be buffered
with a precision op amp such as the OP113 as shown in Figure
37 (shown for the single supply case). This op amp can swing
from 0 V to 4 V on its output while driving a load as small as
600 Ω.
+VS
0.1F
0.1F
VIN RG AD627
REF
0.1F
OP113
0.1F
VOUT
–VS
–VS
Figure 37. Output Buffering
INPUT AND OUTPUT OFFSET ERRORS
The low errors of the AD627 are attributed to two sources,
input and output errors. The output error is divided by G when
referred to the input. In practice, the input errors dominate at
high gains and the output errors dominate at low gains. The
total offset error for a given gain is calculated as:
Total Error RTI = Input Error + (Output Error/Gain)
Total Error RTO = (Input Error × G) + Output Error
RTI offset errors and noise voltages for different gains are shown
below in Table III.
Table III. RTI Error Sources
Max Total
RTI Offset Error
V
V
Max Total
RTI Offset Drift
V/؇C V/؇C
Total RTI Noise
nV/√Hz
Gain AD627A AD627B AD627A AD627B AD627A & AD627B
5 450
250
5
10 350
200
4
20 300
175
3.5
50 270
160
3.2
100 270
155
3.1
500 252
151
3
1000 251
151
3
3
95
2
66
1.5
56
1.2
53
1.1
52
1
52
1
52
Make vs. Buy: A Typical Application Error Budget
The example in Figure 38 serves as a good comparison between
the errors associated with an integrated and a discrete in amp
implementation. A ± 100 mV signal from a resistive bridge
(common-mode voltage = +2.5 V) is to be amplified. This ex-
ample compares the resulting errors from a discrete two op
amp in amp and from the AD627. The discrete implementation
uses a four-resistor precision network (1% match, 50 ppm/°C
tracking).
The errors associated with each implementation are detailed in
Table IV and show the integrated in amp to be more precise,
both at ambient and over temperature. It should be noted that
the discrete implementation is also more expensive. This is pri-
marily due to the relatively high cost of the low drift precision
resistor network.
Note, the input offset current of the discrete in amp implemen-
tation is the difference in the bias currents of the two op amps,
not the offset currents of the individual op amps. Also, while the
values of the resistor network are chosen so that the inverting
and noninverting inputs of each op amp see the same impedance
(about 350 Ω), the offset current of each op amp will add an
additional error which must be characterized.
Errors Due to AC CMRR
In Table IV, the error due to common-mode rejection is the
error that results from the common-mode voltage from the
bridge 2.5 V. The ac error due to nonideal common-mode
rejection cannot be calculated without knowing the size of the ac
common-mode voltage (usually interference from 50 Hz/60 Hz
mains frequencies).
A mismatch of 0.1% between the four gain setting resistors will
determine the low frequency CMRR of a two op amp in amp.
The plot in Figure 38 shows the practical results, at ambient
temperature, of resistor mismatch. The CMRR of the circuit in
Figure 39 (Gain = 11) was measured using four resistors which
–12–
REV. A
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