AD6659 查看數據表（PDF） - Analog Devices
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AD6659 Datasheet PDF : 40 Pages
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Input Clock Divider
The AD6659 contains an input clock divider with the ability
to divide the input clock by integer values from 1 to 6.
Optimum performance is obtained by enabling the internal
DCS when using divide ratios other than 1, 2, or 4.
The AD6659 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow
the clock divider to be resynchronized on every SYNC signal
or only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have
their clock dividers aligned to guarantee simultaneous input
sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance
is required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD6659 contains a DCS that retimes the nonsampling
(falling) edge, providing an internal clock signal with a nominal
50% duty cycle. This allows the user to provide a wide range of
clock input duty cycles without affecting the performance of the
AD6659. Noise and distortion performance are nearly flat for a
wide range of duty cycles with the DCS on, as shown in Figure 42.
80
75
DCS ON
70
65
60
DCS OFF
55
50
45
40
10
20
30
40
50
60
70
80
POSITIVE DUTY CYCLE (%)
Figure 42. SNR vs. DCS On/Off
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz nominal. The loop has a time constant associated with
it that must be considered in applications in which the clock
rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after the dynamic clock frequency increases or decreases
before the DCS loop is relocked to the input signal.
AD6659
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR from the low frequency
SNR (SNRLF) at a given input frequency (fINPUT) due to jitter
(tJRMS) can be calculated by
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 (−SNRLF /10) ]
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 43.
80
75
0.05ps
70
0.2ps
65
60
0.5ps
55
1.0ps
50
1.5ps
2.0ps
45
3.0ps 2.5ps
1
10
100
1k
FREQUENCY (MHz)
Figure 43. SNR vs. Input Frequency and Jitter
Treat the clock input as an analog signal in cases in which
aperture jitter may affect the dynamic range of the AD6659. To
avoid modulating the clock signal with digital noise, keep
power supplies for clock drivers separate from the ADC output
driver supplies. Low jitter, crystal controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock at the last step.
For more information, see the AN-501 Application Note and the
AN-756 Application Note, available at www.analog.com.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 44, the analog core power dissipated by the
AD6659 is proportional to its sample rate. The digital power
dissipation of the CMOS outputs is determined primarily by the
strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (26 bits, in the case of the
AD6659).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency of fCLK/2. In practice, the DRVDD current
is established by the average number of output bits switching,
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