AD6659 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD6659

Dual IF Receiver

Analog Devices 

AD6659

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 7

Timing Specifications .................................................................. 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Equivalent Circuits ......................................................................... 14

Theory of Operation ...................................................................... 16

ADC Architecture ...................................................................... 16

Analog Input Considerations.................................................... 16

Voltage Reference ....................................................................... 19

Clock Input Considerations ...................................................... 20

Power Dissipation and Standby Mode..................................... 21

REVISION HISTORY

2/10―Rev. 0 to Rev. A

Changes to Title ................................................................................ 1

Changes to Features Section............................................................ 1

Changes to General Description Section ...................................... 3

1/10—Revision 0: Initial Version

Digital Outputs ........................................................................... 22

Timing ......................................................................................... 22

Built-In Self-Test and Output Test ............................................... 24

BIST.............................................................................................. 24

Output Test Modes..................................................................... 24

Channel/Chip Synchronization.................................................... 25

Noise Shaping Requantizer (NSR) ............................................... 26

20% BW NSR Mode (16 MHz BW at 80 MSPS) .................... 26

DC and Quadrature Error Correction (QEC)............................ 27

Serial Port Interface (SPI).............................................................. 29

Configuration Using the SPI..................................................... 29

Hardware Interface..................................................................... 30

Configuration Without the SPI ................................................ 30

SPI Accessible Features.............................................................. 30

Memory Map .................................................................................. 31

Reading the Memory Map Register Table............................... 31

Open Locations .......................................................................... 31

Default Values ............................................................................. 31

Memory Map Register Table..................................................... 32

Memory Map Register Descriptions........................................ 35

Applications Information .............................................................. 37

Design Guidelines ...................................................................... 37

Outline Dimensions ....................................................................... 38

Ordering Guide .......................................................................... 38

Rev. A | Page 2 of 40

Share Link: