AD723 查看數據表（PDF） - Analog Devices
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AD723 Datasheet PDF : 20 Pages
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AD723
HSYNC/VSYNC
(USER INPUTS)
RIN/GIN BIN
(USER INPUTS)
MODULATOR
RESTORE
INPUT
CLAMPS
BURST FLAG/
DELAY LINE RESET
Y
C
tSW
tSB
tSM
tSR
tRW
tSD
tDW
tSS
tSC
tMW
tBY
tBC
Figure 6. Timing Diagram (Not to Scale)
Table I. Timing Description (See Figure 6)
Symbol
Name
Description
NTSC1
tSW
Sync Width
Input valid sync width for burst
insertion (user-controlled).
Min
2.8 µs
Max
5.3 µs
tSB
Sync to Blanking
Minimum sync to color delay
End
(user-controlled).
Min
8.2 µs
tSM
Sync to Modulator Delay to modulator clamp start.
Restore
8.4 µs
tMW
Modulator Restore Length of modulator offset clamp
Width
(no chroma during this period).
1.1 µs
tSR
Sync to RGB DC
Delay to input clamping start.
Restore
5.4 ms
tRW
DC Restore Width Length of input clamp (no RGB
response during this period).
2.5 µs
tSD
Sync to Delay Line Delay to start of delay line
Reset
clock reset.
5.7 µs
tDW
Delay Line Reset
Length of delay line clock reset
Width
(no luma response during this
period), also burst gate.
2.5 µs
tSS
Sync Input to Luma Delay from sync input assertion
Typ
310 ns
Sync Output
to sync in LUMA output.
tBY
Blanking End to
Delay from RGB input assertion
Typ
340 ns
LUMA Start
to LUMA output response.
tSC
Sync to Colorburst Delay from valid horizontal sync
Typ
5.8 µs
start to CRMA colorburst output.
tBC
Blanking End to
Delay from RGB input assertion
CRMA Start
to CRMA output response.
Typ
360 ns
NOTES
1Input clock = 14.318180 MHz, STND pin = logic high.
2Input clock = 17.734475 MHz, STND pin = logic low.
PAL2
Min
3.3 µs
Max
5.4 µs
Min
8.1 µs
8.3 µs
0.9 µs
5.6 ms
2.3 µs
5.8 µs
2.3 µs
Typ
265 ns
Typ
280 ns
Typ
5.9 µs
Typ
300 ns
–12–
REV. 0
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