AD7280A
100nF
VDD(n – 1)
7
FERRITE
100nF
VDD0
100nF
10µF
100nF
VDDn
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
100nF
100nF
100nF
100nF
100nF
100nF
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0
AD7280A
1kΩ
VDDn
VREG
DVCC
AVCC
1µF
0.1µF
VDRIVE
1kΩ
ALERT
1kΩ
SDO
MASTER
10kΩ
VREF
CREF
1µF
0.1µF
VDD1
22pF
22pF
22pF
22pF
22pF
22pF
22pF
VDD(n – 1)
10µF 100nF
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
100nF
100nF
100nF
100nF
100nF
100nF
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0
AD7280A
3
22pF
22pF
22pF
22pF
2
22pF
22pF
VDD0
22pF
10µF 100nF
10kΩ
5
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
100nF
100nF
100nF
100nF
100nF
100nF
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0
VSS0
AD7280A
0.1µF
1µF
VREG
DVCC
AVCC
VDRIVE
ALERT
SDO
MASTER
VREF
CREF
0.1µF
1kΩ
1kΩ
10kΩ
1µF
0.1µF
VDD0
4
6
VREG
DVCC
AVCC
VDRIVE
ALERT
CNVST
PD
SDO
SCLK
SDI
CS
1kΩ
0.1µF
1µF
NOTES
1
ALL AD7280A DEVICES ON THE DAISY CHAIN
SHOULD BE LOCATED ON THE SAME PCB.
2 PLACE 22pF DAISY-CHAIN CAPACITORS
AS CLOSE AS POSSIBLE TO THEIR
TERMINATING PINS, THAT IS, CLOSE TO
THE PIN THAT HAS THE ARROW POINTING
TO IT ON THE DIAGRAM.
3 ROUTE VDD AND VSS TRACES TO ENSURE
A LOW IMPEDANCE CONNECTION BETWEEN THEM.
4 ROUTE DAISY-CHAIN TRACKS ON AN INNER
PCB LAYER.
5 ADD A VSS PLANE FROM THE UPPER SLAVE
DEVICE EXTENDED DOWN OVER AND UNDER
THE DAISY CHAIN TO ACT AS A SHIELD FOR
THE DAISY CHAIN.
6 PLACE AD7280A PARTS AS CLOSE TOGETHER
AS POSSIBLE ON THE BOARD TO MINIMIZE
THE LENGTH OF THE DAISY-CHAIN TRACKS.
7 FERRITES ON THE VDD LINES CAN BE REPLACED
WITH 20Ω RESISTORS EXCEPT IN THE CASE OF THE
VSS0 CONNECTION. IN THIS CASE, THE 20Ω RESISTOR
SHOULD BE REPLACED WITH A 0Ω RESISTOR.
1µF
OPTIONAL INTERFACE PINS
DSP/MICRO-
PROCESSOR
4-WIRE SPI INTERFACE
Figure 29. AD7280A Daisy-Chain Configuration
Rev. 0 | Page 18 of 48