AD7495ARMZ-REEL7 查看數據表（PDF） - Analog Devices
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AD7495ARMZ-REEL7 Datasheet PDF : 24 Pages
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AD7475/AD7495
SERIAL INTERFACE
Figure 26 shows the detailed timing diagram for serial inter-
facing to the AD7475/AD7495. The serial clock provides the
conversion clock and also controls the transfer of information
from the AD7475/AD7495 during conversion.
CS initiates the data transfer and conversion process. The falling
edge of CS puts the track-and-hold into hold mode and takes
the bus out of three-state. The analog input is sampled at this
point.
The conversion is also initiated at this point and requires
16 SCLK cycles to complete. Once 13 SCLK falling edges have
elapsed, the track-and-hold goes back into track on the next
SCLK rising edge, as shown in Figure 26 at Point B. On the 16th
SCLK falling edge, the SDATA line goes back into three-state.
If the rising edge of CS occurs before 16 SCLKs have elapsed,
the conversion is terminated and the SDATA line goes back
into three-state, as shown in Figure 27; otherwise SDATA
returns to three-state on the 16th SCLK falling edge, as shown
in Figure 26.
Sixteen serial clock cycles are required to perform the con-
version process and to access data from the AD7475/AD7495.
CS going low provides the first leading zero to be read in by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges beginning with the second
leading zero; thus the first falling clock edge on the serial clock
has the second leading zero provided. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked out
on the previous (15th) falling edge.
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge, although the first leading zero
still has to be read on the first SCLK falling edge after the CS
falling edge. Therefore, the first rising edge of SCLK after the
CS falling edge provides the second leading zero and the 15th
rising SCLK edge has DB0 provided. This method may not
work with most microprocessors/DSPs, but could possibly be
used with FPGAs and ASICs.
CS
SCLK
t2
1
2
3
t3
SDATA
0
THREE-STATE
0
0
0
FOUR LEADING ZEROS
tCONVERT
t6
4
5
t4
DB11
t7
DB10
B
13
14
t5
15
16
t8
tQUIET
DB2
DB1
DB0
THREE-STATE
Figure 26. Serial Interface Timing Diagram
CS
SCLK
t2
1
t3
SDATA
0
THREE-STATE
2
3
0
0
0
FOUR LEADING ZEROS
tCONVERT
t6
4
5
t4
DB11
t7
DB10
B
13
14
t9
DB2
15
16
tQUIET
THREE-STATE
Figure 27. Serial Interface Timing Diagram — Conversion Termination
Rev. B | Page 20 of 24
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