AD7490BCPZ-REEL7 查看數據表（PDF） - Analog Devices

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AD7490BCPZ-REEL7

16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP

Analog Devices 

AD7490

Data Sheet

Auto Shutdown (PM1 = 0, PM0 = 1)

In this mode, the AD7490 automatically enters shutdown at the

end of each conversion when the control register is updated.

When the part is in shutdown, the track-and-hold is in hold

mode. Figure 24 shows the general diagram of the operation of

the AD7490 in this mode.

In shutdown mode, all internal circuitry on the AD7490 is

powered down. The part retains information in the control

register during shutdown. The AD7490 remains in shutdown

until the next CS falling edge it receives. On this CS falling edge,

the track-and-hold that was on hold while the part was in shut-

down mode returns to track-and-hold. Wake-up time from auto

shutdown is 1 μs, and the user should ensure that 1 μs elapses

before attempting a valid conversion. When running the AD7490

with a 20 MHz clock, one dummy cycle of 16 × SCLK should be

sufficient to ensure the part is fully powered up. During this

dummy cycle, the contents of the control register should remain

unchanged; therefore, the WRITE bit should be 0 on the DIN

line. This dummy cycle effectively halves the throughput rate of

the part, with every other conversion result being valid. In this

mode, the power consumption of the part is greatly reduced

with the part entering shutdown at the end of each conversion.

When the control register is programmed to move into auto

shutdown, it does so at the end of the conversion. The user can

move the ADC in and out of the low power state by controlling

the CS signal.

PART ENTERS

SHUTDOWN ON CS

RISING EDGE AS

PM1 = 0, PM0 = 1

PART BEGINS

TO POWER

UP ON CS

FALLING EDGE

Auto Standby (PM1 = PM0 = 0)

In this mode, the AD7490 automatically enters standby mode at

the end of each conversion when the control register is updated.

Figure 25 shows the general diagram of the operation of the

AD7490 in this mode. When the part is in standby, portions of

the AD7490 are powered-down, but the on-chip bias generator

remains powered up. The part retains information in the control

register during standby. The AD7490 remains in standby until it

receives the next CS falling edge. On this CS falling edge, the

track-and-hold that was on hold while the part was in standby

returns to track. Wake-up time from standby is 1 μs; the user

should ensure that 1 μs elapses before attempting a valid conver-

sion on the part in this mode. When running the AD7490 with

a 20 MHz clock, one dummy cycle of 16 × SCLK should be

sufficient to ensure the part is fully powered up. During this

dummy cycle, the contents of the control register should remain

unchanged; therefore, the WRITE bit should be set to 0 on the

DIN line. This dummy cycle effectively halves the throughput

rate of the part with every other conversion result being valid.

In this mode, the power consumption of the part is greatly

reduced with the part entering standby at the end of each con-

version. When the control register is programmed to move into

auto standby, it does so at the end of the conversion. The user

can move the ADC in and out of the low power state by

controlling the CS signal.

PART IS FULLY

POWERED UP

PART ENTERS

SHUTDOWN ON CS

RISING EDGE AS

PM1 = 0, PM0 = 1

CS

SCLK

DOUT

1

16

CHANNE L IDENTIFIER BITS + CONVERSION RESULT

DUMMY CONVERSION

1

16

INVALID DATA

1

16

CHANNE L IDENTIFIER BITS + CONVERSION RESULT

DIN

DATA IN TO CONTROL/SHADOW REGISTER

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCKS, PM1 = 0, PM0 = 1

CONTROL REGISTER CONTENTS SHOULD

NOT CHANGE, WRITE BIT = 0

Figure 24. Auto Shutdown Mode Operation

DATA IN TO CONTROL/SHADOW REGISTER

TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1

IN CONTROL REGISTER OR SET WRITE BIT = 0

CS

SCLK

DOUT

DIN

PART ENTERS

STANDBY ON CS

RISING EDGE AS

PM1 = 0, PM0 = 0

PART BEGINS

TO POWER

UP ON CS

FALLING EDGE

PART IS FULLY

POWERED UP

PART ENTERS

STANDBY ON CS

RISING EDGE AS

PM1 = 0, PM0 = 0

DUMMY CONVERSION

1

12

16

1

12

16

1

12

16

CHANNE L IDENTIFIER BITS + CONVERSION RESULT

DATA IN TO CONTROL/SHADOW REGISTER

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCKS, PM1 = 0, PM0 = 0

INVALID DATA

CONTROL REGISTER CONTENTS SHOULD

REMAIN UNCHANGED, WRITE BIT = 0

Figure 25. Auto Standby Mode Operation

Rev. D | Page 20 of 28

CHANNE L IDENTIFIER BITS + CONVERSION RESULT

DATA IN TO CONTROL/SHADOW REGISTER

TO KEEP PART IN THIS MODE, LOAD PM1 = 0,

PM0 = 0 IN CONTROL REGISTER

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