AD7492AR-REEL7 查看數據表（PDF） - Analog Devices
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AD7492AR-REEL7 Datasheet PDF : 24 Pages
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AD7492
111...111
111...110
111...000
011...111
1LSB = VREF/4096
000...010
000...001
000...000
0V 1/2LSB
+VREF –1LSB
ANALOG INPUT
Figure 16. Transfer Characteristic for 12 Bits
AC ACQUISITION TIME
In ac applications, it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of
the ADC. Large values of impedance at the VIN pin of the ADC
cause the THD to degrade at high input frequencies.
Table 6. Dynamic Performance Specifications
Input
SNR
THD
Typical Amplifier Current
Buffers 500 kHz 500 kHz Consumption
AD9631 69.5
80
17 mA
AD797 69.6
81.6
8.2 mA
DC ACQUISITION TIME
The ADC starts a new acquisition phase at the end of a
conversion and ends it on the falling edge of the CONVST
signal. At the end of the conversion, there is a settling time
associated with the sampling circuit. This settling time lasts
120 ns. The analog signal on VIN is also acquired during this
settling time; therefore, the minimum acquisition time needed
is 120 ns.
Figure 17 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R3
represents the source impedance of a buffer amplifier or
resistive network, R1 is an internal switch resistance, R2 is for
bandwidth control, and C1 is the sampling capacitor. C2 is
back-plate capacitance and switch parasitic capacitance.
During the acquisition phase the sampling capacitor must be
charged to within 0.5 LSB of its final value.
R3
VIN
R1
125Ω
C1
22pF
C2
R2
8pF
636Ω
Figure 17. Equivalent Analog Input Circuit
ANALOG INPUT
Figure 18 shows the equivalent circuit of the analog input
structure of the AD7492. The two diodes, D1 and D2, provide
ESD protection for the analog inputs. The Capacitor C3 is
typically about 4 pF and can be primarily attributed to pin
capacitance. The Resistor R1 is an internal switch resistance.
This resistor is typically about 125 Ω. The Capacitor C1 is the
sampling capacitor while R2 is used for bandwidth control.
VIN
C3
4pF
VDD
D1
D2
R1
125Ω
C2
8pF
C1
22pF
R2
636Ω
Figure 18. Equivalent Analog Input Circuit
PARALLEL INTERFACE
The parallel interface of the AD7492 is 12 bits wide. The output
data buffers are activated when both CS and RD are logic low. At
this point the contents of the data register are placed onto the data
bus. Figure 19 shows the timing diagram for the parallel port.
Figure 20 shows the timing diagram for the parallel port when
CS and RD are tied permanently low. In this setup, once the
BUSY line goes from high to low, the conversion process is
completed. The data is available on the output bus slightly
before the falling edge of BUSY.
Note that the data bus cannot change state while the A/D is
doing a conversion, as this would have a detrimental effect on
the conversion in progress. The data out lines go three-state
again when either the RD or CS line goes high. Thus the CS can
be tied low permanently, leaving the RD line to control
conversion result access. Please reference the VDRIVE section for
output voltage levels.
OPERATING MODES
The AD7492 has two possible modes of operation depending
on the state of the CONVST pulse at the end of a conversion,
Mode 1 and Mode 2.
Mode 1 (High-Speed Sampling)
In this mode of operation the CONVST pulse is brought high
before the end of conversion, that is, before BUSY goes low (see
Figure 20). If the CONVST pin is brought from high-to-low
while BUSY is high, the conversion is restarted. When
operating in this mode a new conversion should not be initiated
until 140 ns after BUSY goes low. This acquisition time allows
the track/hold circuit to accurately acquire the input signal. As
mentioned earlier, a read should not be done during a
conversion. This mode facilitates the fastest throughput times
for the AD7492.
Rev. A | Page 14 of 24
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