AD7492BR 查看數據表（PDF） - Analog Devices

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AD7492BR

1.25 MSPS, 16 mW Internal REF and CLK, 12-Bit Parallel ADC

Analog Devices 

ADSP-21065Lto AD7492 Interface

Figure 30 shows a typical interface between the AD7492 and the

ADSP-21065L SHARC® processor. This interface is an example

of one of three DMA handshake modes. The MSX control line is

actually three memory select lines. Internal ADDR25–24 are

decoded into MS3-0, these lines are then asserted as chip selects.

The DMAR1 (DMA Request 1) is used in this setup as the

interrupt to signal end of conversion. The rest of the interface is

standard handshaking operation.

OPTIONAL

ADDR0 TO

ADDR23

MSX

ADSP-21065L1

DMAR1

RD

ADDRESS BUS

ADDRESS

LATCH

ADDRESS

BUS

ADDRESS

DECODER

D0 TO 31

DATA BUS

CONVST

AD7492

CS

BUSY

RD

DB0 TO DB9

(DB11)

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 30. ADSP-21065L to AD7492 Interface

TMS320C25 to AD7492 Interface

Figure 31 shows an interface between the AD7492 and the

TMS320C25. The CONVST signal can be applied from the

TMS320C25 or from an external source. The BUSY line

interrupts the digital signal processor when conversion is

completed. The TMS320C25 does not have a separate RD

output to drive the AD7492 RD input directly. This has to be

generated from the processor STRB and R/W outputs with the

addition of some glue logic. The RD signal is OR-gated with the

MSC signal to provide the WAIT state required in the read cycle

for correct interface timing. The following instruction is used to

read the conversion from the AD7492:

IN D,ADC

where:

D is the data memory address.

ADC is the AD7492 address.

The read operation must not be attempted during conversion.

AD7492

OPTIONAL

A0 TO A15

TMS320C251

IS

ADDRESS BUS

ADDRESS

DECODER

CONVST

AD7492

CS

STRB

R/W

BUSY

RD

READY

MSC

DMD0 TO DMD15

DATA BUS

DB0 TO DB9

(DB11)

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 31. TMS320C25 to AD7492 Interface

PIC17C4x to AD7492 Interface

Figure 32 shows a typical parallel interface between the AD7492

and PIC17C4x. The microcontroller sees the ADC as another

memory device with its own specific memory address on the

memory map. The CONVST signal can be controlled by either

the microcontroller or an external source. The BUSY signal

provides an interrupt request to the microcontroller when a

conversion ends. The INT pin on the PIC17C4x must be

configured to be active on the negative edge. Port C and Port D

of the microcontroller are bidirectional and used to address the

AD7492 and to read in the 12-bit data. The OE pin on the PIC

can be used to enable the output buffers on the AD7492 and

perform a read operation.

OPTIONAL

PIC17C4x1

AD0 TO AD15

CONVST

DB0 TO DB9

(DB11)

AD7492

ALE

OE

INT

ADDRESS

LATCH

ADDRESS

DECODER

CS

RD

BUSY

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 32. PIC17C4x to AD7492 Interface

Rev. A | Page 19 of 24

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