AD7476AYRM 查看數據表（PDF） - Analog Devices
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AD7476AYRM Datasheet PDF : 24 Pages
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AD7476A/AD7477A/AD7478A
time is another cycle, i.e., 1 µs, the AD7476A/AD7477A/
AD7478A can be said to dissipate 17.5 mW for 2 µs during each
conversion cycle. If the throughput rate is 100 kSPS, the cycle time is
10 µs and the average power dissipated during each cycle is
(2/10) ϫ (17.5 mW) = 3.5 mW. If VDD = 3 V, SCLK = 20 MHz,
and the devices are again in power-down mode between conver-
sions, then the power dissipation during normal operation is
5.1 mW. The AD7476A/AD7477A/AD7478A can now be said
to dissipate 5.1 mW for 2 µs during each conversion cycle. With
a throughput rate of 100 kSPS, the average power dissipated
during each cycle is (2/10) ϫ (5.1 mW) = 1.02 mW. Figure 12
shows the power versus the throughput rate when using the
power-down mode between conversions with both 5 V and 3 V
supplies.
The power-down mode is intended for use with throughput
rates of approximately 333 kSPS and under, since at higher
sampling rates there is no power saving made by using the
power-down mode.
100
VDD = 5V, SCLK = 20MHz
10
1
VDD = 3V, SCLK = 20MHz
0.1
0.01
0
50
100
150
200
250
300
350
THROUGHPUT – kSPS
SERIAL INTERFACE
Figures 13, 14, and 15 show the detailed timing diagrams for
serial interfacing to the AD7476A, AD7477A, and AD7478A,
respectively. The serial clock provides the conversion clock and
also controls the transfer of information from the AD7476A/
AD7477A/AD7478A during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode and
takes the bus out of three-state; the analog input is sampled at this
point. Also, the conversion is initiated at this point.
For the AD7476A, the conversion will require 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-and-
hold will go back into track on the next SCLK rising edge, as shown
in Figure 13 at Point B. On the 16th SCLK falling edge, the SDATA
line will go back into three-state. If the rising edge of CS occurs
before 16 SCLKs have elapsed, the conversion will be terminated
and the SDATA line will go back into three-state; otherwise, SDATA
returns to three-state on the 16th SCLK falling edge, as shown in
Figure 13. Sixteen serial clock cycles are required to perform the
conversion process and to access data from the AD7476A.
For the AD7477A, the conversion will require 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold will go back into track on the next rising edge as
shown in Figure 14 at Point B. If the rising edge of CS occurs
before 14 SCLKs have elapsed, the conversion will be terminated
and the SDATA line will go back into three-state. If 16 SCLKs
are considered in the cycle, SDATA will return to three-state on
the 16th SCLK falling edge, as shown in Figure 14.
For the AD7478A, the conversion will require 12 SCLK cycles
to complete. The track-and-hold will go back into track on the
rising edge after the 11th falling edge, as shown in Figure 15 at
Point B. If the rising edge of CS occurs before 12 SCLKs have
Figure 12. Power vs. Throughput
CS
SCLK
tCONVERT
t2
t6
1
2
3
4
5
SDATA
THREE-
STATE
t3
Z ZERO
ZERO
t4
ZERO
4 LEADING ZEROS
DB11
t7
DB10
t1
B
13
14
t5
15
16
t8
DB2
DB1
DB0
tQUIET
THREE-STATE
1/THROUGHPUT
Figure 13. AD7476A Serial Interface Timing Diagram
CS
SCLK
SDATA
THREE-STATE
t2
1
2
3
tCONVERT
t6
4
5
t3
Z ZERO
ZERO
ZERO
4 LEADING ZEROS
t4
DB9
t7
DB8
t1
B
13
14
t5
15
16
t8
tQUIET
DB0
ZERO ZERO
2 TRAILING ZEROS
THREE-STATE
1/ THROUGHPUT
Figure 14. AD7477A Serial Interface Timing Diagram
–18–
REV. C
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