AD8158 查看數據表（PDF） - Analog Devices

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AD8158

6.5 Gbps Quad Buffer Mux/Demux

Analog Devices 

AD8158

Pin No.

95

96

97

98

99

100

Mnemonic

SEL3

SEL2

SEL1

SEL0

BICAST

SEL4G

Type

Control1

Control1

Control1

Control1

Control1

Control1

Description

Lane 3 A/B Switch Control

Lane 2 A/B Switch Control

Lane 1 A/B Switch Control

Lane 0 A/B Switch Control

Enable Bicast Mode for Port A and Port B Outputs

Set Transmitter for Low Speed PE

1 Logic level of control pins referred to DVCC.

2 EQ control pins (EQ_A0, EQ_A1, EQ_B0, EQ_B1, EQ_C0, EQ_C1) require 5 kΩ in series when DVCC > VCC.

Rev. 0 | Page 8 of 36

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