AD9139(Rev0) 查看數據表（PDF） - Analog Devices
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AD9139 Datasheet PDF : 56 Pages
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Data Sheet
AD9139
DATA FORMAT SELECT REGISTER
Address: 0x26, Reset: 0x00, Name: DATA_FORMAT_SEL
Table 55. Bit Descriptions for DATA_FORMAT_SEL
Bit No. Bit Name
Settings Description
7
DATA_FORMAT
Select binary or twos complement data format.
0 Input data in twos complement format.
1 Input data in binary format.
0
DATA_BUS_WIDTH
Data interface mode. See the LVDS Input Data Ports section for
information about the operation of the different interface modes.
0 Word mode; 16-bit interface bus width.
1 Byte mode; 8-bit interface bus width.
Reset
0
Access
R/W
0
R/W
DATAPATH CONTROL REGISTER
Address: 0x27, Reset: 0x00, Name: DATAPATH_CTRL
Table 56. Bit Descriptions for DATAPATH_CTRL
Bit No. Bit Name
Settings
7
INVSINC_ENABLE
5
DIG_GAIN_DCOFFSET_ENABLE
Description
Enable the inverse sinc filter.
Enable digital gain adjustment and dc offset.
Reset
0
0
Access
RW
RW
INTERPOLATION CONTROL REGISTER
Address: 0x28, Reset: 0x00, Name: INTERPOLATION_CTRL
Table 57. Bit Descriptions for INTERPOLATION_CTRL
Bit No. Bit Name
Settings Description
7
INTERPOLATION_MODE
Interpolation mode selection.
0 2× mode.
1 1× mode.
Reset
0x0
Access
RW
POWER-DOWN DATA INPUT 0 REGISTER
Address: 0x39, Reset: 0x00, Name: LVDS_IN_PWR_DOWN_0
Table 58. Bit Descriptions for LVDS_IN_PWR_DOWN_0
Bit No. Bit Name
Settings Description
[3:0] PWR_DOWN_DATA_INPUT_BITS
Powers down Data Input Bits[3:0]. Each bit controls one data
input bit. These bits can be powered down individually.
Reset Access
0x0 R/W
DAC DC OFFSET 0 REGISTER
Address: 0x3B, Reset: 0x00, Name: DAC_DC_OFFSET0
Table 59. Bit Descriptions for DAC_DC_OFFSET0
Bit No. Bit Name
Settings Description
[7:0] DAC_DC_OFFSET_LSB
See Register 0x3C.
Reset Access
0x00 RW
DAC DC OFFSET 1 REGISTER
Address: 0x3C, Reset: 0x00, Name: DAC_DC_OFFSET1
Table 60. Bit Descriptions for DAC_DC_OFFSET1
Bit No. Bit Name
Settings Description
[7:0] DAC_DC_OFFSET_MSB
DAC DC offset, Bits[15:0], is a dc value that is added directly to the
sample values written to the DAC.
Reset Access
0x00 RW
Rev. 0 | Page 51 of 56
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