AD9230-210 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD9230-210 Datasheet PDF : 21 Pages
| |||
AD9230
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9230.
These transients can degrade the converter’s dynamic performance.
The AD9230 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are
valid on the rising edge of DCO.
The lowest typical conversion rate of the AD9230 is 40 MSPS.
At clock rates below 1 MSPS, the AD9230 will assume standby
mode.
RBIAS
The AD9230 requires the user to place a 10KΩ resistor between
the RBIAS pin and ground. This resister should have a 1%
tolerance, and is used to set the master current reference of the
ADC core.
AD9230 CONFIGURATION USING THE SPI
The AD9230 serial port interface allows the user to configure
the converter for specific functions or operations through a
structured register space inside the ADC. This gives the user
added flexibility to customize device operation depending on
the application. Addresses are accessed (programmed or read
back) serially in one-byte words. Each byte may be further
divided down into fields which are documented in the Memory
Map Section below.
There are three pins that define the serial port interface or SPI
to this particular ADC. They are the SPI SCLK / DFS, SPI SDIO
/ DCS, and CSB pins. The SCLK/DFS (serial clock) is used to
synchronize the read and write data presented the ADC.. The
SDIO / DCS (serial data input/output) is a dual purpose pin
that allows data to be sent and read from the internal ADC
memory map registers. The CSB or chip select bar is an active
low control that enables or disables the read and write cycles.
See Table X.
Table X. Serial Port Pins
Pin Function
SCLK SCLK (Serial Clock) is the serial shift clock in. SCLK is
used to synchronize serial interface reads and writes.
SDIO SDIO (Serial Data Input/Output) is a dual purpose pin.
The typical role for this pin is an input and output
depending on the instruction being sent and the
relative position in the timing frame.
CSB CSB (Chip Select Bar) is active low controls that gates
the read and write cycles.
RESET Master device reset. When asserted, device assumes
default settings.
The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure X
and Table X. Table X. SPI Timing Diagram specifications
Preliminary Technical Data
Spec
Name
tDS
tDH
tCLK
tS
tH
tHI
tLO
Meaning
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high
state
Minimum period that SCLK should be in a logic low
state
During an instruction phase a 16bit instruction is transmitted.
Data then follows the instruction phase and is determined by
the W0 and W1 bits which is 1 or more bytes of data. All data is
composed of 8bit words. The first bit of each individual byte of
serial data indicates whether this is a read or write command.
This allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
Data may be sent in MSB or in LSB first mode. MSB first is
default on power up and may be changed by changing the
configuration register. For more information about this feature
and others see SPI Doc at www.analog.com.
Rev. PrE | Page 18 of 21
Share Link: 