AD9845AJST 查看數據表（PDF） - Analog Devices

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AD9845AJST

Mixed-Signal Front-End (MxFE) Processor for Broadband Communications

Analog Devices 

SERIAL

3

INTERFACE

3V

ANALOG SUPPLY

0.1␮F

1.0␮F

1.0␮F

0.1␮F

AD9845A

48 47 46 45 44 43 42 41 40 39 38 37

D0 1

AUX1IN

36

OBSOLETE DATA 12

OUTPUTS

D1 2

D2 3

D3 4

D4 5

D5 6

D6

7

D7

8

D8

9

D9

10

D10

11

(MSB) D11

12

PIN 1

IDENTIFIER

AD9845A

TOP VIEW

(Not to Scale)

AVSS

35

AUX2IN

34

AVDD2

33

BYP4

32

31 NC

30 CCDIN

29 BYP2

BYP1

28

AVDD1

27

AVSS

26

AVSS

25

13 14 15 16 17 18 19 20 21 22 23 24

0.1␮F

0.1␮F

3V

ANALOG SUPPLY

0.1␮F

0.1␮F

CCD SIGNAL

0.1␮F

0.1␮F

3V

ANALOG SUPPLY

3V

DRIVER

SUPPLY

0.1␮F

NC = NO CONNECT

8

CLOCK

INPUTS

0.1␮F

3V

ANALOG SUPPLY

Figure 33. Recommended Circuit Configuration for CCD-Mode

Internal Power-On Reset Circuitry

After power-on, the AD9845A will automatically reset all inter-

nal registers and perform internal calibration procedures. This

takes approximately 1 ms to complete. During this time, normal

clock signals and serial write operations may occur. However,

serial register writes will be ignored until the internal reset opera-

tion is completed. Pin 43 (formerly RSTB on the AD984x non-A

products) is no longer used for the reset operation. Toggling Pin

43 in the AD9845A will have no effect.

Grounding and Decoupling Recommendations

As shown in Figure 33, a single ground plane is recommended

for the AD9845A. This ground plane should be as continuous

as possible, particularly around Pins 25 through 39. This will

ensure that all analog decoupling capacitors provide the lowest

possible impedance path between the power and bypass pins and

their respective ground pins. All decoupling capacitors should

be located as close as possible to the package pins. A single clean

power supply is recommended for the AD9845A, but a separate

digital driver supply may be used for DRVDD (Pin 13). DRVDD

should always be decoupled to DRVSS (Pin 14), which should

be connected to the analog ground plane. Advantages of using

a separate digital driver supply include using a lower voltage

(2.7 V) to match levels with a 2.7 V ASIC, reducing digital power

dissipation, and reducing potential noise coupling. If the digital

outputs (Pins 3–12) must drive a load larger than 20 pF, buffer-

ing is recommended to reduce digital code transition noise.

Alternatively, placing series resistors close to the digital out-

put pins may also help reduce noise.

REV. 0

–21–

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