ADD8754ACPZ-REEL 查看數據表（PDF） - Analog Devices
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ADD8754ACPZ-REEL Datasheet PDF : 28 Pages
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VCOM AMPLIFIER
The output of the VCOM amplifier is designed to control the
voltage on the VCOM plane of the LCD display. The VCOM
amplifier is designed to source and sink the capacitive pulse
current and ensure stable operation with high load capacitance.
Input Overvoltage Protection
Whenever the input exceeds the supply voltage, attention must
be paid to the input overvoltage characteristics. When an
overvoltage occurs, the amplifier can be damaged, depending
on the voltage level and the magnitude of the fault current.
When the input voltage exceeds the supply voltage by more
than 0.6 V, the internal pin junctions allow current to flow from
the input to the supplies. This input current is not inherently
damaging to the device, provided it is 5 mA or less.
Short-Circuit Output Conditions
The VCOM amplifier does not have internal short-circuit protection
circuitry. As a precaution, do not short the output directly to the
positive power supply or to the ground.
GATE PULSE MODULATOR CIRCUIT
The gate pulse modulator is used for LCD applications in which
shaping of the gate high voltage signal improves image quality.
A charge pump is used to generate the on voltage, VGH. A lower
gate voltage level, VDD_1, is desired during the last portion of
the gate’s on time and is provided by VOUT. The integrated gate
pulse modulator circuit provides control over the slope and delay
of the transition between these two TFT on-voltage levels.
The gate pulse modulator circuit has four input pins (VGH,
VDD_1, VDPM, and VFLK) and one output pin (VGH_M).
VFLK is a digital control signal, usually provided by the timing
controller, whose high or low level determines which of the two
input voltages, VGH or VDD_1, is passed through to VGH_M.
The gate high modulator circuit becomes active when the voltage
on pin VDPM exceeds the turn-on threshold value of 2.2 V.
When the control voltage VFLK switches from logic low to logic
high during normal operation with VDPM at logic high (see
Figure 21), the output voltage VGH_M transitions from VDD_1
to VGH. When the control voltage VFK switches from logic
high to logic low, the output voltage VGH_M transitions from
VGH to VDD_1 after a time delay determined by the size of a
capacitor from the CE pin to the GND and a slew rate
determined by the size of resistor from the RE pin to the GND.
ADD8754
The delay capacitance in farad is calculated using the following
equation:
CE = (Delay Time) × 0.000238
The RE in ohms is calculated using the following equation:
( ) RE =
302
− 5000
Slew Rate × Load Capacitance
When the voltage on the VDPM pin is less than the turn-on
threshold value, the CE pin is internally connected to GND to
discharge the delay capacitor.
VDPM
VFLK
GATE HIGH
VIN_1 MOD. CIRCUIT
L
S1
O
G
S3
I
C
S2
GND
S4
GND
REF
VGH
VGH_M
CL
VDD_1
VOUT/VGH
DELAY CE
CAPACITOR
RAMP RE
RESISTOR
GND
Figure 20. Gate Pulse Modulator Functional Block Diagram
ENABLE – VDPM
LOW
CONTROL SIGNAL – VFLK
LOW
T1
OUTPUT SIGNAL – VGH_M
WITH LOAD
CAPACITANCE CL
LOW
T1
DELAY CONTROLLED
BY CE
SLOPE CONTROLLED BY RE
T2
VGH
VDD_1
T2
Figure 21. Gate Pulse Modulator Timing Diagram
Rev. 0 | Page 16 of 28
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