ADF7011 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
ADF7011 Datasheet PDF : 24 Pages
| |||
ADF7011
0.00
0.20
0.50
0.0
25 – j2.6
433MHz
1.00
2.00
5.00
؊0.20
؊5.00
؊150
؊140
؊130
؊0.50
16 – j33
868MHz
؊30
؊40
؊2.00
؊50
؊120
؊1.00
؊60
؊110
؊70
؊100 ؊90 ؊80
Figure 10. Output Impedance on Smith Chart
Fractional-N
N Counter and Error Correction
The ADF7011 consists of a 15-bit ⌺-⌬ fractional-N divider.
The N Counter divides the output frequency to the output
stage back to the PFD frequency. It consists of a prescaler,
integer, and fractional part.
The prescaler can be 4/5 or 8/9. A prescaler setting of 8/9 is
recommended for 868 MHz operation. A prescaler setting of
4/5 is recommended for 433 MHz operation.
The output frequency of the PLL is
(8 × Fractional) + Error
PFD Frequency × Int +
215
REFERENCE IN
،R
PFD/
CHARGE
PUMP
VCO
،N
THIRD ORDER
⌺-⌬ MODULATOR
FRACTIONAL-N
INTEGER-N
Figure 11. Fractional-N PLL
Fractional-N Registers
The fractional part is made up of a 15-bit divide, made up of a
12-bit N value in the N register summed with a 10-bit value
(plus sign bit) in the R register that is used for error correction,
as shown in Figure 12.
M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1
12-BIT N VALUE
The resolution of each register is the smallest amount that the
output frequency can be changed by changing the LSB of the
register.
Changing the Output Frequency
The fractional part of the N register changes the output fre-
quency by
PFD Frequency × Fractional Register Value
212
The frequency error correction contained in the R register
changes the output frequency by
PFD Frequency × Error CorrectionRegister Value
215
By default, this will be set to 0. The user can calibrate the system
and set this by writing a twos complement number to Bits F1–F11
in the R register. This can be used to compensate for initial error,
temperature drift, and aging effects in the crystal reference.
Integer-N Register
The integer part of the N Counter contains the prescaler and A
and B Counters. It is eight bits wide and offers a divide of
P2 + 3P + 3 to 255.
The combination of the integer (255) and the fractional (31767/
31768) gives a maximum N Divider of 256. The minimum
usable PFD is
Maximum Required Output Frequency
(255 + 1)
For use in the European 868 MHz to 870 MHz band, there is a
restriction to using a minimum PFD of 3.4 MHz to allow the
user to have a center frequency of 870 MHz.
PFD Frequency
The PFD frequency is the number of times a comparison is
made between the reference frequency and the feedback signal
from the output.
The higher the PFD frequency, the more often a comparison is
made at the PFD. This means that the frequency lock time will
be reduced when jumping from one frequency to another by
increasing the PFD. Having a PFD of > 5 MHz will reduce the
available output power due to EN300-220 spurious regulations.
؎ F10 F9 F8 F7 F6 F5 F4 F3 F2 F1
10-BIT (؉ SIGN) ERROR CORRECTION
N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
15-BIT FRACTIONAL N REGISTER
Figure 12. Fractional Components
–18–
REV. 0
Share Link: 