ADF7020-1 查看數據表（PDF） - Analog Devices

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ADF7020-1

High Performance FSK/ASK Transceiver IC

Analog Devices 

ADF7020-1

Parameter

Min

PHASE-LOCKED LOOP

VCO Gain

Phase Noise (In-Band)

Normalized In-Band Phase Noise

Floor 9

Phase Noise (Out-of-Band)

Residual FM

PLL Settling

Typ

40

35

16.5

−89

−198

−110

128

40

REFERENCE INPUT

Crystal Reference

External Oscillator

Load Capacitance

Crystal Start-Up Time

Input Level

ADC PARAMETERS

INL

DNL

TIMING INFORMATION

Chip Enabled to Regulator Ready

Chip Enabled to RSSI Ready

Tx-to-Rx Turnaround Time

LOGIC INPUTS

Input High Voltage, VINH

Input Low Voltage, VINL

Input Current, IINH/IINL

Input Capacitance, CIN

Control Clock Input

LOGIC OUTPUTS

Output High Voltage, VOH

Output Low Voltage, VOL

CLKOUT Rise/Fall

CLKOUT Load

TEMPERATURE RANGE—TA

3.625

3.625

33

2.1

1.0

±1

±1

10

3.0

150 μs +

(5 × TBIT)

0.7 × V DD

DVDD − 0.4

−40

Max

Unit

Test Conditions

MHz/V

MHz/V

MHz/V

dBc/Hz

dBc/Hz

433 MHz, VCO adjust = 0,

VCO_BIAS_SETTING = 2

315 MHz, VCO adjust = 0,

VCO_BIAS_SETTING = 2

135 MHz, VCO adjust = 0,

VCO_BIAS_SETTING = 1

PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz,

FRF = 315 MHz, VCO_BIAS_SETTING = 2

dBc/Hz

Hz

μs

1 MHz offset

From 200 Hz to 20 kHz, FRF = 315 MHz

Measured for a 10 MHz frequency step to

within 5 ppm accuracy, PFD = 20 MHz,

LBW = 50 kHz

24

MHz

Must ensure PFD maximum is not exceeded

24

MHz

pF

Refer to the crystal’s data sheet

ms

11.0592 MHz crystal, using 33 pF load

capacitors

ms

Using 16 pF load capacitors

CMOS

levels

See the Reference Input section

LSB

From 2.3 V to 3.6 V, TA = 25°C

LSB

From 2.3 V to 3.6 V, TA = 25°C

μs

CREG = 100 nF

ms

See Table 13 for more details

Time to synchronized data out, includes

AGC settling. See AGC Information and

Timing section for more details.

V

0.2 × V DD V

±1

μA

10

pF

50

MHz

V

IOH = 500 μA

0.4

V

IOL = 500 μA

5

ns

10

pF

+85

°C

Rev. 0 | Page 6 of 48

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