ADG3300 查看數據表（PDF） - Analog Devices

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ADG3300

Low Voltage 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translator

Analog Devices 

ADG3300

TERMINOLOGY

Table 4.

Symbol

VIHA

VILA

VOHA

VOLA

RA,HiZ

VIHY

VILY

VOHY

VOLY

CY

ILY, HiZ

VIHEN

VILEN

CEN

ILEN

tEN

tP, A-Y

tR, A-Y

tF, A-Y

DMAX, A-Y

tSKEW, A-Y

tPPSKEW, A-Y

tP, Y-A

tR, Y-A

tF, Y-A

DMAX, Y-A

tSKEW, Y-A

tPPSKEW, Y-A

VCCA

VCCY

ICCA

ICCY

IHiZA

IHiZY

Description

Logic input high voltage at Pins A1 to A8.

Logic input low voltage at Pins A1 to A8.

Logic output high voltage at Pins A1 to A8.

Logic output low voltage at Pins A1 to A8.

Pull-down resistance measured at Pins A1 to A8 when EN = 0.

Logic input high voltage at Pins Y1 to Y8.

Logic input low voltage at Pins Y1 to Y8.

Logic output high voltage at Pins Y1 to Y8.

Logic output low voltage at Pins Y1 to Y8.

Capacitance measured at Pins Y1 to Y8 (EN = 0).

Leakage current at Pins Y1 to Y8 when EN = 0 (high impedance state at Pins Y1 to Y8).

Logic input high voltage at the EN pin.

Logic input low voltage at the EN pin.

Capacitance measured at EN pin.

Enable (EN) pin leakage curent.

Three-state enable time for Pins Y1 to Y8.

Propagation delay when translating logic levels in the A Y direction.

Rise time when translating logic levels in the A Y direction.

Fall time when translating logic levels in the A Y direction.

Guaranteed data rate when translating logic levels in the A Y direction under the driving and loading conditions

specified in Table 1.

Difference between propagation delays on any two channels when translating logic levels in the A Y direction.

Difference in propagation delay between any one channel and the same channel on a different part (under the

same driving/loading conditions) when translating logic levels in the A Y direction.

Propagation delay when translating logic levels in the Y A direction.

Rise time when translating logic levels in the Y A direction.

Fall time when translating logic levels in the Y A direction.

Guaranteed data rate when translating logic levels in the Y A direction under the driving and loading conditions

specified in Table 1.

Difference between propagation delays on any two channels when translating logic levels in the Y A direction.

Difference in propagation delay between any one channel and the same channel on a different part (under the

same driving/loading conditions) when translating in the Y A direction.

VCCA supply voltage.

VCCY supply voltage.

VCCA supply current.

VCCY supply current.

VCCA supply current during three-state mode (EN = 0).

VCCY supply current during three-state mode (EN = 0).

Rev. 0 | Page 14 of 20

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