ADG3300 查看數據表（PDF） - Analog Devices

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ADG3300

Low Voltage 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translator

Analog Devices 

THEORY OF OPERATION

The ADG3300 level translator allows the level shifting necessary

for data transfer in a system where multiple supply voltages are

used. The device requires two supplies, VCCA and VCCY (VCCA ≤

VCCY). These supplies set the logic levels on each side of the

device. When driving the A pins, the device translates the VCCA-

compatible logic levels to VCCY-compatible logic levels available

at the Y pins. Similarly, since the device is capable of bidirectional

translation, when driving the Y pins, the VCCY-compatible logic

levels are translated to VCCA-compatible logic levels available at

the A pins. When EN = 0, the A1 to A8 are internally pulled

down with 6 kΩ resistors while Y1 to Y8 pins are three-stated.

When EN is driven high, the ADG3300 goes into normal

operation mode and performs level translation.

LEVEL TRANSLATOR ARCHITECTURE

The ADG3300 consists of eight bidirectional channels. Each

channel can translate logic levels in either the A Y or the Y A

direction. It uses a one-shot accelerator architecture, which

ensures excellent switching characteristics. Figure 35 shows a

simplified block diagram of a bidirectional channel.

VCCA

VCCY

T1

T2

6kΩ

U1 U2

P

A

ONE-SHOT GENERATOR N

Y

6kΩ

U4 U3

T4

T3

Figure 35. Simplified Block Diagram of an ADG3300 Channel

The logic level translation in the A Y direction is performed

using a level translator (U1) and an inverter (U2), and the

translation in the Y A direction is performed using the inverters

U3 and U4. The one-shot generator detects a rising or falling

edge present on either the A side or the Y side of the channel. It

sends a short pulse that turns on the PMOS transistors (T1–T2)

for a rising edge, or the NMOS transistors (T3–T4) for a falling

edge. This charges/discharges the capacitive load faster, which

results in fast rise and fall times.

The inputs of the unused channels (A or Y) should be tied to

their corresponding VCC rail (VCCA or VCCY) or to GND.

ADG3300

INPUT DRIVING REQUIREMENTS

To ensure correct operation of the ADG3300, the circuit that

drives the input of an ADG3300 channels should have an output

impedance of less than or equal to 150 Ω and a minimum

current driving capability of 36 mA.

OUTPUT LOAD REQUIREMENTS

The ADG3300 level translator is designed to drive CMOS-

compatible loads. If current driving capability is required, it is

recommended to use buffers between the ADG3300 outputs

and the load.

ENABLE OPERATION

The ADG3300 provides three-state operation at the Y I/O pins

by using the enable (EN) pin as shown in Table 5.

Table 5. Truth Table

EN

Y I/O Pins

0

Hi-Z1

1

Normal operation2

A I/O Pins

6 kΩ pull-down to GND

Normal operation2

1 High impedance state.

2 In normal operation, the ADG3300 performs level translation.

When EN = 0, the ADG3300 enters into three-state mode. In

this mode the current consumption from both the VCCA and

VCCY supplies is reduced, allowing the user to save power, which

is critical, especially for battery-operated systems. The EN input

pin can be driven with either VCCA- or VCCY-compatible logic

levels.

POWER SUPPLIES

For proper operation of the ADG3300, the voltage applied to

the VCCA must always be less than or equal to the voltage applied

to VCCY. To meet this condition, the recommended power-up

sequence is VCCY first and then VCCA. The ADG3300 operates

properly only after both supply voltages reach their nominal

values. It is not recommended to use the part in a system where

VCCA might be greater than VCCY during power-up due to a sig-

nificant increase in the current taken from the VCCA supply. For

optimum performance, the VCCA and VCCY pins should be

decoupled to GND as close as possible to the device.

Rev. 0 | Page 15 of 20

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