ADG3300 查看數據表（PDF） - Analog Devices

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ADG3300

Low Voltage 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translator

Analog Devices 

APPLICATIONS

The ADG3300 is designed for digital circuits that operate at

different supply voltages; therefore, logic level translation is

required. The lower voltage logic signals are connected to the

A pins, and the higher voltage logic signals are connected to the

Y pins. The ADG3300 can provide level translation in both

directions from A Y and Y A on all eight channels, eliminating

the need for a level translator IC for each direction. The internal

architecture allows the ADG3300 to perform bidirectional level

translation without an additional signal to set the direction of

the translation. It also allows simultaneous data flow in both

directions on the same part, for example, four channels translate

in the A Y direction while the other four translate in the Y A

direction. This simplifies the design by eliminating the timing

requirements for the direction signal and reduces the number of

ICs used for level translation.

Figure 36 shows an application where a 1.8 V microprocessor

can read or write data to or from a 3.3 V peripheral device using

an 8-bit bus.

1.8V

I/OL1

I/OL2

I/OL3

MICROPROCESSOR/ I/OL4

MICROCONTROLLER/

DSP

I/OL5

I/OL6

I/OL7

I/OL8

GND

100nF

100nF

A1

VCCA

A2

Y1

VCCY

Y2

A3

Y3

A4

Y4

ADG3300

A5

Y5

A6

Y6

A7

Y7

A8

Y8

EN

GND

I/OH1 3.3V

I/OH2

I/OH3

I/OH4

I/OH5

PERIPHERAL

DEVICE

I/OH6

I/OH7

I/OH8

GND

Figure 36. 1.8 V to 3.3 V 8-Bit Level Translation Circuit

When the application requires level translation between a

microprocessor and multiple peripheral devices, the ADG3300

Y I/O pins (Y1 to Y8) can be three-stated by setting EN = 0.

This feature allows the ADG3300 to share the data buses with

ADG3300

other devices without causing contention issues. Figure 37 shows

an application where a 3.3 V microprocessor is connected to

1.8 V peripheral devices using the three-state feature.

3.3V

I/OH1

I/OH2

I/OH3

MICROPROCESSOR/ I/OH4

MICROCONTROLLER/

DSP

I/OH5

I/OH6

I/OH7

I/OH8

GND

CS

100nF

100nF

Y1

VCCY

Y2

A1

VCCA

A2

Y3

A3

ADG3300

Y4

A4

Y5

A5

Y6

A6

Y7

A7

Y8

A8

GND

EN

I/OL1 1.8V

I/OL 2

I/OL 3

I/OL 4

I/OL 5

I/OL 6

I/OL 7

I/OL 8

GND

PERIPHERAL

DEVICE 1

100nF

100nF

Y1

A1

VCCY

VCCA

Y2

A2

Y3

A3

ADG3300

Y4

A4

Y5

A5

Y6

A6

Y7

A7

Y8

A8

GND

EN

I/OL1 1.8V

I/OL 2

I/OL 3

I/OL 4

I/OL 5

I/OL 6

I/OL 7

I/OL 8

GND

PERIPHERAL

DEVICE 2

Figure 37. 1.8 V to 3.3 V Level Translation Circuit

Using the Three-State Feature

LAYOUT GUIDELINES

As with any high speed digital IC, the printed circuit board

layout is important in the overall circuit performance. Care

should be taken to ensure proper power supply bypass and

return paths for the high speed signals. Each VCC pin (VCCA and

VCCY) should be bypassed using low effective series resistance

(ESR) and effective series inductance (ESI) capacitors placed as

close as possible to the VCCA and VCCY pins. The parasitic induc-

tance of the high speed signal track might cause significant

overshoot. This effect can be reduced by keeping the length

of the tracks as short as possible. A solid copper plane for the

return path (GND) is also recommended.

Rev. 0 | Page 17 of 20

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