ADM1067ASU-REEL 查看數據表（PDF） - Analog Devices

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ADM1067ASU-REEL

Super Sequencer® with Open-Loop Margining DACs

Analog Devices 

ADM1067

Parameter

Gain Error

Maximum Load Current (Source)

Maximum Load Current (Sink)

Maximum Load Capacitance

Settling Time into 50 pF Load

Load Regulation

PSRR

REFERENCE OUTPUT

Reference Output Voltage

Load Regulation

Minimum Load Capacitance

PSRR

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge Pump) Mode

(PDO1 to PDO6)

Output Impedance

VOH

IOUTAVG

Standard (Digital Output) Mode

(PDO1 to PDO10)

VOH

VOL

IOL 2

ISINK2

RPULL-UP

ISOURCE (VPn)2

Min Typ

100

100

2.5

60

40

2.043

1

2.048

−0.25

0.25

60

500

11 12.5

10.5 12

20

2.4

VPU −

0.3

0

16 20

Three-State Output Leakage Current

Oscillator Frequency

90 100

DIGITAL INPUTS (VXn, A0, A1, MUP, MDN)

Input High Voltage, VIH

2.0

Input Low Voltage, VIL

Input High Current, IIH

−1

Input Low Current, IIL

Input Capacitance

5

Programmable Pull-Down Current,

20

IPULL-DOWN

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, VIH

2.0

Input Low Voltage, VIL

Output Low Voltage, VOL2

SERIAL BUS TIMING

Clock Frequency, fSCLK

Bus Free Time, tBUF

4.7

Start Setup Time, tSU;STA

4.7

Start Hold Time, tHD;STA

4

SCL Low Time, tLOW

4.7

Max Unit Test Conditions/Comments

1

%

μA

μA

50 pF

2

μs

mV Per mA

dB DC

dB 100 mV step in 20 ns with 50 pF load

2.053 V

mV

mV

μF

dB

No load

Sourcing current, IDACnMAX = −100 μA

Sinking current, IDACnMAX = 100 μA

Capacitor required for decoupling, stability

DC

kΩ

14

V

IOH = 0

13.5 V

IOH = 1 μA

μA 2 V < VOH < 7 V

V

4.5 V

V

VPU (pull-up to VDDCAP or VPn) = 2.7 V, IOH = 0.5 mA

VPU to VPn = 6.0 V, IOH = 0 mA

VPU ≤ 2.7 V, IOH = 0.5 mA

0.50 V

IOL = 20 mA

20 mA Maximum sink current per PDO pin

60 mA Maximum total sink for all PDOs

29 kΩ Internal pull-up

2

mA Current load on any VPn pull-ups, that is, total source current

available through any number of PDO pull-up switches

configured onto any one

10

μA VPDO = 14.4 V

110 kHz All on-chip time delays derived from this clock

V

Maximum VIN = 5.5 V

0.8 V

Maximum VIN = 5.5 V

μA VIN = 5.5 V

1

μA VIN = 0

pF

μA VDDCAP = 4.75, TA = 25°C, if known logic state is required

V

0.8 V

0.4 V

IOUT = −3.0 mA

400 kHz

μs

μs

μs

μs

Rev. B | Page 5 of 32

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