ADM1027ARQ-REEL 查看數據表（PDF） - ON Semiconductor

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ADM1027ARQ-REEL

dBCOOL™ Remote Thermal Controller and Voltage Monitor

ON Semiconductor 

ADM1027

Table XXIV. XOR Tree Test Enable

Register Address

0x6F

R/W

Read/Write

Description

XOR Tree Test Enable Register

Power-On Default

0x00

<0>

XEN

If the XEN bit is set to 1, the device enters the XOR tree test mode. Clearing the bit

removes the device from the XOR tree test mode.

<7:1>

Reserved

Unused. Do not write to these bits.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register

will have no effect.

Register Address

0x70

<7:0>

R/W

Read/Write

Read/Write

Table XXV. Remote 1 Temperature Offset

Description

Remote 1 Temperature Offset

Power-On Default

0x00

Allows a twos complement offset value to be automatically added to or subtracted from

the Remote 1 temperature reading. This is to compensate for any inherent system offsets

such as PCB trace resistance. LSB value = 1oC.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register

will have no effect.

Register Address

0x71

<7:0>

R/W

Read/Write

Read/Write

Table XXVI. Local Temperature Offset

Description

Local Temperature Offset

Power-On Default

0x00

Allows a twos complement offset value to be automatically added to or subtracted from

the local temperature reading. LSB value = 1oC.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register

will have no effect.

Register Address

0x72

<7:0>

R/W

Read/Write

Read/Write

Table XXVII. Remote 2 Temperature Offset

Description

Remote 2 Temperature Offset

Power-On Default

0x00

Allows a twos complement offset value to be automatically added to or subtracted from

the Remote 2 temperature reading. This is to compensate for any inherent system off-

sets such as PCB trace resistance. LSB value = 1oC.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register

will have no effect.

REV. A

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