ADM690 查看數據表（PDF） - Analog Devices

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ADM690

Microprocessor Supervisory Circuits

Analog Devices 

ADM690–ADM695

R =(VCC – 50 mV)/1 µA

Note that the resistor will discharge the battery slightly. With a

VCC supply of 4.5 V, a suitable resistor is 4.3 MΩ. With a 3 V

battery this will draw around 700 nA. This will be negligible in

most cases.

BATTERY

VBATT

R

ADM69x

+5V

R1

R2

+

BATTERY

VCC

VOUT

PFI

ADM690

ADM692

ADM694

VBATT

RESET

PFO

GND WDI

0.1µF

µP POWER

CMOS RAM

POWER

µP SYSTEM

µP RESET

µP NMI

I/O LINE

Figure 22b. Preventing Spurious RESETS During Battery

Replacement

TYPICAL APPLICATIONS

ADM690, ADM692 AND ADM694

Figure 23 shows the ADM690/ADM692/ADM694 in a typical

power monitoring, battery backup application. VOUT powers the

CMOS RAM. Under normal operating conditions with VCC

present, VOUT is internally connected to VCC. If a power failure

occurs, VCC will decay and VOUT will be switched to VBATT

thereby maintaining power for the CMOS RAM. A RESET

pulse is also generated when VCC falls below 4.65 V for the

ADM690/ADM694 or 4.4 V for the ADM692. RESET will

remain low for 50 ms (200 ms for ADM694) after VCC returns

to 5 V.

The watchdog timer input (WDI) monitors an I/O line from the

µP system. This line must be toggled once every 1.6 seconds to

verify correct software execution. Failure to toggle the line indi-

cates that the µP system is not correctly executing its program

and may be tied up in an endless loop. If this happens, a reset

pulse is generated to initialize the processor.

If the watchdog timer is not needed, the WDI input should be

left floating.

The Power Fail Input, PFI, monitors the input power supply via

a resistive divider network. The voltage on the PFI input is com-

pared with a precision 1.3 V internal reference. If the input volt-

age drops below 1.3 V, a power fail output (PFO) signal is

generated. This warns of an impending power failure and may

be used to interrupt the processor so that the system may be

shut down in an orderly fashion. The resistors in the sensing

network are ratioed to give the desired power fail threshold

voltage VT.

VT = (1.3 R1/R2) + 1.3 V

R1/R2 = (VT/1.3) – 1

Figure 23a. ADM690/ADM692/ADM694 Typical Application

Circuit A

Figure 23b shows a similar application but in this case the PFI

input monitors the unregulated input to the 7805 voltage regu-

lator. This gives an earlier warning of an impending power fail-

ure. It is useful with processors operating at low speeds or

where there are a significant number of housekeeping tasks to be

completed before the power is lost.

INPUT

POWER

V > 8V

R1

R2

BATTERY

+5V

7805

0.1µF

VCC

VOUT

PFI

ADM690

ADM692

ADM694

VBATT

RESET

PFO

GND WDI

0.1µF

µP POWER

CMOS RAM

POWER

µP SYSTEM

µP RESET

µP NMI

I/O LINE

Figure 23b. ADM690/ADM692/ADM694 Typical Application

Circuit B

ADM691, ADM693, ADM695

A typical connection for the ADM691/ADM693/ADM695 is

shown in Figure 24. CMOS RAM is powered from VOUT. When

5 V power is present this is routed to VOUT. If VCC fails then

VBATT is routed to VOUT. VOUT can supply up to 100 mA from

VCC, but if more current is required, an external PNP transistor

can be added. When VCC is higher than VBATT, the BATT ON

output goes low, providing up to 25 mA of base drive for the

external transistor. A 0.1 µF capacitor is connected to VOUT to

supply the transient currents for CMOS RAM. When VCC is

lower than VBATT, an internal 20 Ω MOSFET connects the

backup battery to VOUT.

–12–

REV. A

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