ADN2811 查看數據表（PDF） - Analog Devices

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ADN2811

OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

ADN2811

ADN2811

PIN

+

QUANTIZER

0

NIN

50Ω 50Ω

VREF

1

50Ω 50Ω

FROM

QUANTIZER

OUTPUT

1

CDR

RETIMED

DATA

CLK

0

VCC

TDINP/N

LOOPEN BYPASS DATAOUTP/N

CLKOUTP/N SQUELCH

Figure 18. Test Modes

SQUELCH MODE

When the squelch input is driven to a TTL high state, both the

clock and data outputs are set to the zero state to suppress

downstream processing. If desired, this pin can be directly

driven by the LOS detector output, SDOUT. If the squelch

function is not required, the pin should be tied to VEE.

TEST MODES: BYPASS AND LOOPBACK

When the bypass input is driven to a TTL high state, the

quantizer output is connected directly to the buffers driving the

data out pins, thus bypassing the clock recovery circuit (see

Figure 18). This feature can help the system deal with

nonstandard bit rates.

The loopback mode can be invoked by driving the LOOPEN

pin to a TTL high state, which facilitates system diagnostic

testing. This connects the test inputs (TDINP/N) to the clock

and data recovery circuit (per Figure 18). The test inputs have

internal 50 Ω terminations and can be left floating when not in

use. TDINP/N are CML inputs and can only be dc-coupled

when being driven by CML outputs. The TDINP/N inputs must

be ac-coupled if being driven by anything other than CML

outputs. Bypass and loopback modes are mutually exclusive.

Only one of these modes can be used at any given time. The

ADN2811 is put into an indeterminate state if the BYPASS and

LOOPEN pins are set to Logic 1 at the same time.

Rev. B | Page 14 of 20

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